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| SIO10N268 Advanced Notebook I/O for ISA or LPC Designs with X-Bus Interface for I/O, Memory, and FWH Emulation and Four Serial Ports Datasheet Product Features * * * 3.3 Volt Operation (5 Volt Tolerant) PC99, PC01, ACPI 1.0 Compliant LPC or ISA Interface SIO10N268 offers two modes of operation: LPC Mode or ISA Mode. These modes are jumper selectable. Three chip selects (2 I/O and 1 Memory) 8-bit data transfers Support for up to 2MB Flash Interfaces with 3V memory devices Support for up to two external I/O components Offers three modes of operation for I/O devices Provides FWH Emulation * Floppy Disk Available on Parallel Port Pins (ACPI Compliant) Enhanced Digital Data Separator 2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps, 250 Kbps Data Rates Programmable Precompensation Modes Four Full Function Serial Ports High Speed NS16C550 Compatible UARTs with Send/Receive 16-Byte FIFOs Supports 230k and 460k Baud Programmable Baud Rate Generator Modem Control Circuitry 480 Address and 15 IRQ Options IrDA v1.2 (4Mbps), HPSIR, ASKIR, Consumer IR Support 2 IR Ports 96 Base I/O Address, 15 IRQ, and 4 DMA Options Standard Mode IBM PC/XT, PC/AT, and PS/2 Compatible Bi-directional Parallel Port Enhanced Parallel Port (EPP) Compatible - EPP 1.7 and EPP 1.9 (IEEE 1284 Compliant) IEEE 1284 Compliant Enhanced Capabilities Port (ECP) ChiProtect Circuitry for Protection 480 Address, Up to 15 IRQ, and Four DMA Options * X-Bus Interface (LPC Mode Only) - * Serial Ports - * * * * * Serial IRQ Compatible with Serialized IRQ Support for PCI Systems Programmable Wake-up Event (PME) Interface (33) General Purpose Input/Output Pins System Management Interrupt 2.88MB Super I/O Floppy Disk Controller Licensed CMOS 765B Floppy Disk Controller Software and Register Compatible with SMSC's Proprietary 82077AA Compatible Core Supports Two Floppy Drives Directly Configurable Open Drain/Push-Pull Output Drivers Supports Vertical Recording Format 16-Byte Data FIFO 100% IBM Compatibility Detects All Overrun and Underrun Conditions Sophisticated Power Control Circuitry (PCC) Including Multiple Power Down Modes for Reduced Power Consumption DMA Enable Logic Data Rate and Drive Control Registers 480 Address, Up to 15 IRQ and Four DMA Options * Infrared Communications Controller - * Multi-Mode Parallel Port with ChiProtect - * * * Two LED Drivers with blinking options Watch Dog Timer with optional output pin 128 Pin TQFP package, VTQN package (green, lead-free) - SMSC SIO10N268 Page 1 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet ORDERING INFORMATION Order Number(s): SIO10N268-NE for 128 pin TQFP package SIO10N268-NU for 128 pin VTQN package (green, lead-free) 80 Arkay Drive Hauppauge, NY 11788 (631) 435-6000 FAX (631) 273-3123 Copyright (c) SMSC 2005. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC's website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems Corporation ("SMSC"). Product names and company names are the trademarks of their respective holders. SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Rev. 0.5 (03-24-05) Page 2 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet TABLE OF CONTENTS Chapter 1 Chapter 2 2.1 2.2 General Description ........................................................................................................... 13 Pin Layouts ......................................................................................................................... 14 LPC Mode ......................................................................................................................................... 14 ISA Mode........................................................................................................................................... 15 Chapter 3 Chapter 4 4.1 4.2 Pin Configurations for SIO10N268 .................................................................................. 16 Description of Pin Functions ............................................................................................. 18 Buffer Type Description..................................................................................................................... 28 Design Guidelines for Implemented Buffer Types ............................................................................ 28 Chapter 5 Chapter 6 Chapter 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 8.1 8.2 8.3 Block Diagram.................................................................................................................... 29 3.3 Volt Operation / 5 Volt Tolerance .............................................................................. 30 Power Functionality ........................................................................................................... 31 VCC Power........................................................................................................................................ 31 VTR Support...................................................................................................................................... 31 32.768 kHz Trickle Clock Input ......................................................................................................... 31 Internal PWRGOOD .......................................................................................................................... 32 Trickle Power Functionality ............................................................................................................... 32 Maximum Current Values.................................................................................................................. 33 Power Management Events (PME/SCI)............................................................................................ 33 Chapter 8 Functional Description....................................................................................................... 34 Super I/O Registers........................................................................................................................... 34 Host Processor Interface (LPC or ISA) ............................................................................................. 34 LPC Interface (LPC Mode only) ........................................................................................................ 35 8.3.1 LPC Interface Signal Definition ...............................................................................................................35 8.3.2 LPC Cycles .............................................................................................................................................35 8.3.3 LFRAME# Usage....................................................................................................................................36 8.3.4 Field Definitions ......................................................................................................................................36 8.3.4.1 I/O Read and Write Cycles ..............................................................................................................36 8.3.4.2 DMA Read and Write Cycles ...........................................................................................................36 8.3.4.3 Memory Read and Write Cycles ......................................................................................................37 8.3.5 Power Management................................................................................................................................37 8.3.5.1 CLOCKRUN Protocol ......................................................................................................................37 8.3.5.2 LPCPD Protocol ..............................................................................................................................37 8.3.5.3 SYNC Protocol ................................................................................................................................38 8.3.5.4 SYNC Timeout.................................................................................................................................38 8.3.5.5 SYNC Patterns and Maximum Number of SYNCS ..........................................................................38 8.3.5.6 SYNC Error Indication .....................................................................................................................38 8.3.5.7 Reset Policy.....................................................................................................................................39 8.3.6 LPC Transfers ........................................................................................................................................39 8.3.6.1 Wait State Requirements.................................................................................................................39 8.4 FWH Interface (LPC Mode Only) ...................................................................................................... 40 8.4.1 Enabling the FWH Interface....................................................................................................................40 8.4.1.1 MEMEN ...........................................................................................................................................40 8.4.1.2 FWHSEL .........................................................................................................................................40 8.4.2 FWH and LPC Memory Addressing........................................................................................................41 8.4.3 FWH Cycle Types...................................................................................................................................41 8.4.4 Field Definitions ......................................................................................................................................42 8.4.4.1 START.............................................................................................................................................42 8.4.4.2 IDSEL ..............................................................................................................................................42 8.4.4.3 MSIZE .............................................................................................................................................42 8.4.4.4 MADDR ...........................................................................................................................................42 SMSC SIO10N268 Page 3 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet 8.4.4.5 SYNC ..............................................................................................................................................42 8.4.4.6 TAR .................................................................................................................................................42 8.4.4.7 Data.................................................................................................................................................42 8.4.5 Protocol ..................................................................................................................................................43 8.4.5.1 Preamble .........................................................................................................................................43 8.4.6 Read Cycle .............................................................................................................................................43 8.4.6.1 Single Byte ......................................................................................................................................43 8.4.7 Write Cycles............................................................................................................................................44 8.4.7.1 Single Byte ......................................................................................................................................44 8.4.8 Error Reporting .......................................................................................................................................44 8.4.9 FWH Cycle Examples .............................................................................................................................44 8.4.9.1 EXAMPLE 1: FWH 1-Byte Read......................................................................................................44 8.4.9.2 EXAMPLE 2: FWH 1-Byte Write......................................................................................................45 8.5 X-Bus Interface (LPC Mode Only)..................................................................................................... 45 8.5.1 I/O Cycles ...............................................................................................................................................46 8.5.1.1 Conceptual Diagrams of X-Bus I/O interface ...................................................................................47 8.5.2 Memory Cycles .......................................................................................................................................49 8.6 8.7 ISA Interface (ISA Mode Only) .......................................................................................................... 50 8.6.1 AEN signal ..............................................................................................................................................51 Floppy Disk Controller ....................................................................................................................... 51 8.7.1 FDC Internal Registers ...........................................................................................................................52 8.7.1.1 Status Register A (SRA) ..................................................................................................................52 8.7.1.2 Status Register B (SRB) ..................................................................................................................54 8.7.1.3 Digital Output Register (DOR) .........................................................................................................56 8.7.1.4 Tape Drive Register (TDR) ..............................................................................................................57 8.7.1.5 Data Rate Select Register (DSR) ....................................................................................................58 8.7.1.6 Main Status Register (MSR) ............................................................................................................60 8.7.1.7 Data Register (FIFO) .......................................................................................................................61 8.7.1.8 Digital Input Register (DIR)..............................................................................................................62 8.7.1.9 Configuration Control Register (CCR) .............................................................................................63 8.7.2 Status Register Encoding .......................................................................................................................64 8.7.2.1 Reset ...............................................................................................................................................66 8.7.2.2 Modes Of Operation ........................................................................................................................66 8.7.3 DMA Transfers .......................................................................................................................................67 8.7.4 Controller Phases ...................................................................................................................................67 8.7.4.1 Command Phase .............................................................................................................................67 8.7.4.2 Execution Phase..............................................................................................................................67 8.7.4.3 Data Transfer Termination...............................................................................................................68 8.7.4.4 Result Phase ...................................................................................................................................68 8.7.5 Command Set/Descriptions ....................................................................................................................69 8.7.6 Instruction Set.........................................................................................................................................71 8.7.7 Data Transfer Commands ......................................................................................................................79 8.7.7.1 Read Data .......................................................................................................................................79 8.7.7.2 Read Deleted Data ..........................................................................................................................80 8.7.7.3 Read A Track...................................................................................................................................81 8.7.7.4 Write Data........................................................................................................................................82 8.7.7.5 Write Deleted Data ..........................................................................................................................82 8.7.7.6 Verify ...............................................................................................................................................82 8.7.7.7 Format A Track................................................................................................................................83 8.7.8 Control Commands.................................................................................................................................85 8.7.8.1 Read ID ...........................................................................................................................................85 8.7.8.2 Recalibrate ......................................................................................................................................85 8.7.8.3 Seek ................................................................................................................................................85 8.7.8.4 Sense Interrupt Status .....................................................................................................................86 8.7.8.5 Sense Drive Status..........................................................................................................................87 8.7.8.6 Specify.............................................................................................................................................87 8.7.8.7 Configure .........................................................................................................................................87 8.7.8.8 Version ............................................................................................................................................88 8.7.8.9 Relative Seek ..................................................................................................................................88 8.7.8.10 Perpendicular Mode.........................................................................................................................89 Rev. 0.5 (03-24-05) Page 4 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet 8.7.8.11 8.7.8.12 8.7.8.13 Lock.................................................................................................................................................90 Enhanced DUMPREG .....................................................................................................................91 Compatibility ....................................................................................................................................91 8.8 Serial Port (UART) ............................................................................................................................ 91 8.8.1 Register Description ...............................................................................................................................91 8.8.1.1 Receive Buffer Register (RB) ..........................................................................................................92 8.8.1.2 Transmit Buffer Register (TB)..........................................................................................................92 8.8.1.3 Interrupt Enable Register (IER) .......................................................................................................92 8.8.1.4 FIFO Control Register (FCR)...........................................................................................................93 8.8.1.5 Interrupt Identification Register (IIR) ................................................................................................94 8.8.1.6 Line Control Register (LCR) ............................................................................................................95 8.8.1.7 Modem Control Register (MCR) ......................................................................................................97 8.8.1.8 Line Status Register (LSR) ..............................................................................................................98 8.8.1.9 Modem Status Register (MSR)........................................................................................................99 8.8.1.10 Scratchpad Register (SCR) ...........................................................................................................100 8.8.2 Programmable Baud Rate Generator (AND Divisor Latches DLH, DLL) ..............................................100 8.8.3 Effect Of The Reset on Register File ....................................................................................................100 8.8.4 FIFO Interrupt Mode Operation.............................................................................................................100 8.8.5 FIFO Polled Mode Operation ................................................................................................................101 8.8.6 Notes On Serial Port Operation ............................................................................................................108 8.8.6.1 FIFO Mode Operation....................................................................................................................108 8.8.6.2 TX and RX FIFO Operation ...........................................................................................................108 8.9 Infrared Interface ............................................................................................................................. 108 8.9.1 8.9.2 8.9.3 8.9.4 8.9.5 IrDA SIR/FIR and ASKIR ......................................................................................................................109 Consumer IR.........................................................................................................................................109 Hardware Interface ...............................................................................................................................109 IR Half Duplex Turnaround Delay Time ................................................................................................110 IR Transmit Pins ...................................................................................................................................111 IBM XT/AT Compatible, Bi-Directional And EPP Modes ...................................................................113 Data Port .......................................................................................................................................113 Status Port.....................................................................................................................................113 Control Port ...................................................................................................................................114 EPP Address Port..........................................................................................................................115 EPP Data Port 0 ............................................................................................................................115 EPP Data Port 1 ............................................................................................................................115 EPP Data Port 2 ............................................................................................................................115 EPP Data Port 3 ............................................................................................................................115 EPP 1.9 Operation ............................................................................................................................116 Software Constraints .....................................................................................................................116 EPP 1.9 Write ................................................................................................................................116 EPP 1.9 Read................................................................................................................................117 EPP 1.7 Operation ............................................................................................................................117 Software Constraints .....................................................................................................................118 EPP 1.7 Write ................................................................................................................................118 EPP 1.7 Read................................................................................................................................118 Extended Capabilities Parallel Port ...................................................................................................119 Vocabulary ........................................................................................................................................120 ECP Implementation Standard..........................................................................................................121 Description.....................................................................................................................................121 Register Definitions .......................................................................................................................122 Operation ..........................................................................................................................................128 Mode Switching/Software Control..................................................................................................128 ECP Operation ..............................................................................................................................128 Termination from ECP Mode .........................................................................................................129 Command/Data .............................................................................................................................129 Data Compression .........................................................................................................................129 Pin Definition .................................................................................................................................130 LPC Connections...........................................................................................................................130 Interrupts .......................................................................................................................................130 8.10 Parallel Port.................................................................................................................................. 111 8.10.1 8.10.1.1 8.10.1.2 8.10.1.3 8.10.1.4 8.10.1.5 8.10.1.6 8.10.1.7 8.10.1.8 8.10.2 8.10.2.1 8.10.2.2 8.10.2.3 8.10.3 8.10.3.1 8.10.3.2 8.10.3.3 8.10.4 8.10.5 8.10.6 8.10.6.1 8.10.6.2 8.10.7 8.10.7.1 8.10.7.2 8.10.7.3 8.10.7.4 8.10.7.5 8.10.7.6 8.10.7.7 8.10.7.8 SMSC SIO10N268 Page 5 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet 8.10.7.9 FIFO Operation..............................................................................................................................130 8.10.7.10 DMA Transfers ............................................................................................................................131 8.10.7.11 DMA Mode - Transfers from the FIFO to the Host .......................................................................131 8.10.7.12 Programmed I/O Mode or Non-DMA Mode..................................................................................131 8.10.7.13 Programmed I/O - Transfers from the FIFO to the Host ..............................................................131 8.10.7.14 Programmed I/O - Transfers from the Host to the FIFO ..............................................................132 8.10.8 Parallel Port Floppy Disk Controller...................................................................................................132 8.10.8.1 FDC on Parallel Port Pin................................................................................................................133 8.11 8.12 8.13 Watchdog Timer........................................................................................................................... 134 LED Functionality ......................................................................................................................... 135 Power Management ..................................................................................................................... 135 8.13.1 FDC Power Management..................................................................................................................135 8.13.1.1 DSR From Powerdown ..................................................................................................................136 8.13.1.2 Wake Up From Auto Powerdown ..................................................................................................136 8.13.1.3 Register Behavior ..........................................................................................................................136 8.13.1.4 Pin Behavior ..................................................................................................................................136 8.13.1.5 System Interface Pins....................................................................................................................137 8.13.1.6 FDD Interface Pins ........................................................................................................................137 8.13.2 UART Power Management ...............................................................................................................138 8.13.2.1 Exit Auto Powerdown ....................................................................................................................138 8.13.3 Parallel Port.......................................................................................................................................138 8.13.3.1 Exit Auto Powerdown ....................................................................................................................138 8.14 Serial IRQ..................................................................................................................................... 138 8.14.1 Timing Diagrams For SER_IRQ Cycle ..............................................................................................139 8.14.1.1 SER_IRQ Cycle Control ................................................................................................................139 8.14.1.2 SER_IRQ Data Frame ...................................................................................................................140 8.14.1.3 Stop Cycle Control.........................................................................................................................141 8.14.1.4 Latency ..........................................................................................................................................141 8.14.1.5 EOI/ISR Read Latency ..................................................................................................................141 8.14.1.6 AC/DC Specification Issue.............................................................................................................142 8.14.1.7 Reset and Initialization...................................................................................................................142 8.14.2 Routable IRQ Inputs..........................................................................................................................142 8.15 PCI CLKRUN Support.................................................................................................................. 143 Overview ...........................................................................................................................................143 CLKRUN# for Serial IRQ...................................................................................................................143 CLKRUN# for LDRQ# .......................................................................................................................143 Using CLKRUN# ...............................................................................................................................143 GPIO Pins .........................................................................................................................................145 Description ........................................................................................................................................146 GPIO Control.....................................................................................................................................148 GPIO Operation ................................................................................................................................148 GPIO, PME and SMI Functionality ....................................................................................................150 SMI Registers....................................................................................................................................151 PME Registers ..................................................................................................................................152 8.15.1 8.15.2 8.15.3 8.15.4 8.16 General Purpose I/O .................................................................................................................... 145 8.16.1 8.16.2 8.16.3 8.16.4 8.16.5 8.17 8.18 System Management Interrupt (SMI)........................................................................................... 151 PME Support................................................................................................................................ 151 8.17.1 8.18.1 Chapter 9 9.1 9.2 10.1 10.2 Runtime Registers ............................................................................................................ 153 Runtime Registers Block Summary ................................................................................................153 Runtime Registers Block Description.............................................................................................. 154 Chapter 10 Configuration ................................................................................................................ 163 Configuration Access Ports.......................................................................................................... 163 Configuration State ...................................................................................................................... 163 10.2.1 Entering the Configuration State .......................................................................................................163 10.2.2 Configuration Register Programming ................................................................................................163 10.2.3 Exiting the Configuration State..........................................................................................................164 10.2.3.1 Programming Example ..................................................................................................................164 Rev. 0.5 (03-24-05) Page 6 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet 10.2.3.2 Configuration Select Register (CSR) .............................................................................................165 10.3 10.4 Configuration Registers Summary............................................................................................... 165 Configuration Registers Description ............................................................................................167 CR00.................................................................................................................................................167 CR01.................................................................................................................................................168 CR02.................................................................................................................................................169 CR03.................................................................................................................................................170 CR04.................................................................................................................................................170 CR05.................................................................................................................................................171 CR06.................................................................................................................................................172 CR07.................................................................................................................................................173 CR08.................................................................................................................................................174 CR09.................................................................................................................................................174 CR0A ................................................................................................................................................174 CR0B ................................................................................................................................................175 CR0C ................................................................................................................................................176 CR0D ................................................................................................................................................176 CR0E ................................................................................................................................................176 CR0F.................................................................................................................................................177 CR10.................................................................................................................................................177 CR11.................................................................................................................................................177 CR12 - CR13.....................................................................................................................................178 CR14.................................................................................................................................................179 CR15.................................................................................................................................................179 CR16.................................................................................................................................................180 CR17.................................................................................................................................................181 CR18 .................................................................................................................................................181 CR19.................................................................................................................................................182 CR1A ................................................................................................................................................183 CR1B.................................................................................................................................................183 CR1C ................................................................................................................................................184 CR1D ................................................................................................................................................184 CR1E.................................................................................................................................................185 CR1F.................................................................................................................................................185 CR20.................................................................................................................................................186 CR21.................................................................................................................................................187 CR22.................................................................................................................................................187 CR23.................................................................................................................................................188 CR24.................................................................................................................................................188 CR25.................................................................................................................................................189 CR26.................................................................................................................................................189 CR27.................................................................................................................................................190 CR28.................................................................................................................................................190 CR29.................................................................................................................................................191 CR2A ................................................................................................................................................191 CR2B ................................................................................................................................................192 CR2C ................................................................................................................................................192 CR2D ................................................................................................................................................193 CR2E ................................................................................................................................................194 CR2F.................................................................................................................................................194 CR30.................................................................................................................................................194 CR31.................................................................................................................................................195 CR32.................................................................................................................................................195 CR33.................................................................................................................................................196 CR34.................................................................................................................................................196 CR35.................................................................................................................................................197 CR36.................................................................................................................................................197 CR37.................................................................................................................................................198 CR38.................................................................................................................................................198 CR39.................................................................................................................................................199 Page 7 Rev. 0.5 (03-24-05) 10.4.1 10.4.2 10.4.3 10.4.4 10.4.5 10.4.6 10.4.7 10.4.8 10.4.9 10.4.10 10.4.11 10.4.12 10.4.13 10.4.14 10.4.15 10.4.16 10.4.17 10.4.18 10.4.19 10.4.20 10.4.21 10.4.22 10.4.23 10.4.24 10.4.25 10.4.26 10.4.27 10.4.28 10.4.29 10.4.30 10.4.31 10.4.32 10.4.33 10.4.34 10.4.35 10.4.36 10.4.37 10.4.38 10.4.39 10.4.40 10.4.41 10.4.42 10.4.43 10.4.44 10.4.45 10.4.46 10.4.47 10.4.48 10.4.49 10.4.50 10.4.51 10.4.52 10.4.53 10.4.54 10.4.55 10.4.56 10.4.57 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet 10.4.58 10.4.59 10.4.60 10.4.61 10.4.62 10.4.63 10.4.64 10.4.65 10.4.66 10.4.67 10.4.68 10.4.69 10.4.70 10.4.71 10.4.72 10.4.73 10.4.74 10.4.75 10.4.76 10.4.77 10.4.78 10.4.79 CR3A ................................................................................................................................................199 CR3B - CR3F ...................................................................................................................................199 CR40 .................................................................................................................................................200 CR41 .................................................................................................................................................200 CR42 .................................................................................................................................................201 CR43 .................................................................................................................................................201 CR44 .................................................................................................................................................202 CR45 .................................................................................................................................................203 CR46 .................................................................................................................................................204 CR48 .................................................................................................................................................205 CR49 .................................................................................................................................................205 CR4A.................................................................................................................................................206 CR4B.................................................................................................................................................207 CR4C ................................................................................................................................................208 CR4D ................................................................................................................................................209 CR4E.................................................................................................................................................210 CR4F.................................................................................................................................................210 CR50 .................................................................................................................................................211 CR51 .................................................................................................................................................211 CR52 .................................................................................................................................................212 CR53 .................................................................................................................................................212 CR54.................................................................................................................................................213 10.5 10.6 11.1 11.2 12.1 12.2 12.3 12.4 Logical Device Base I/O Address and Range.............................................................................. 215 Note A. Logical Device IRQ and DMA Operation ........................................................................ 217 Chapter 11 Operational Description ............................................................................................... 218 Maximum Guaranteed Ratings .................................................................................................... 218 DC Electrical Characteristics ....................................................................................................... 218 Chapter 12 Timing Diagrams .......................................................................................................... 222 Power-up Timing .......................................................................................................................... 222 Input Clock Timing ....................................................................................................................... 223 LPC Timing (LPC Mode Only) .....................................................................................................224 X-Bus Timing (LPC Mode Only)...................................................................................................226 12.4.1 X-Bus I/O Timing...............................................................................................................................226 12.4.1.1 X-Bus I/O Read Timing..................................................................................................................226 12.4.1.2 X-Bus I/O Write Timing..................................................................................................................227 12.4.2 Representative LPC I/O Cycle to X-Bus Cycle Timing ......................................................................228 12.4.2.1 X-Bus I/O Read Cycle: LPC I/O Read Cycle - Data from X-Bus Device to Host...........................228 12.4.2.2 X-Bus I/O Write Cycle: LPC I/O Write Cycle - Data from Host to X-Bus Device ............................229 12.4.3 X-Bus Memory Cycle Timing.............................................................................................................230 12.4.3.1 Timing For FWH and LPC initiated Memory Read Cycles with the X-Bus .....................................230 12.4.3.2 Timing For FWH and LPC initiated Memory Write Cycles with the X-Bus .....................................231 12.5 12.6 12.7 12.8 Host Timing (ISA Mode Only) ...................................................................................................... 232 Floppy Disk Timing....................................................................................................................... 234 EPP Parallel Port Timing ............................................................................................................. 235 ECP Parallel Port Timing ............................................................................................................. 238 Parallel Port FIFO (Mode 101) ..........................................................................................................238 ECP Parallel Port Timing ..................................................................................................................238 Forward-Idle ......................................................................................................................................238 Forward Data Transfer Phase ...........................................................................................................238 Reverse-Idle Phase...........................................................................................................................238 Reverse Data Transfer Phase...........................................................................................................238 Output Drivers ...................................................................................................................................239 12.8.1 12.8.2 12.8.3 12.8.4 12.8.5 12.8.6 12.8.7 12.9 12.10 12.11 IR Timing...................................................................................................................................... 242 Serial IRQ Timing ..................................................................................................................... 245 UART Timing ............................................................................................................................ 246 Chapter 13 Rev. 0.5 (03-24-05) XNOR-Chain Test Mode.............................................................................................. 247 Page 8 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet 13.1 13.2 13.3 13.4 14.1 Entering and Exiting Test Mode................................................................................................... 247 Pin List of XNOR Chain ............................................................................................................... 248 Setup of XNOR Chain .................................................................................................................. 248 Testing Procedure........................................................................................................................ 249 Chapter 14 Chapter 15 Package Outline ............................................................................................................ 251 References...................................................................................................................... 253 128 Pin TQFP Package Outline, 14x14x1.0 Body, 2 MM Footprint ............................................ 251 LIST OF FIGURES Figure 5.1 - SIO10N268 Block Diagram .......................................................................................................................29 Figure 8.1 - FWH Memory Cycle Preamble..................................................................................................................43 Figure 8.2 - Single Byte Read ......................................................................................................................................43 Figure 8.3 - Single Byte Write ......................................................................................................................................44 Figure 8.4 - X-Bus Interface, Mode 1 ...........................................................................................................................48 Figure 8.5 - X-Bus Interface, Mode 2 ...........................................................................................................................48 Figure 8.6 - X-Bus Interface, Mode 3 ...........................................................................................................................49 Figure 8.7 - Serial Data ................................................................................................................................................95 Figure 8.8 - Infrared Interface Block Diagram ............................................................................................................110 Figure 8.9 - CLKRUN# System Implementation Example ..........................................................................................144 Figure 8.10 - Clock Start Illustration ...........................................................................................................................145 Figure 8.11 - GPIO Function ......................................................................................................................................149 Figure 12.1 - Power-Up Timing ..................................................................................................................................222 Figure 12.2 - 14MHZ Clock Timing............................................................................................................................223 Figure 12.3 - PCI Clock Timing .................................................................................................................................223 Figure 12.4 - Reset Timing.........................................................................................................................................224 Figure 12.5 - Output Timing Measurement Conditions, LPC Signals .........................................................................224 Figure 12.6 - Input Timing Measurement Conditions, LPC Signals ...........................................................................224 Figure 12.7 - I/O Write................................................................................................................................................225 Figure 12.8 - I/O Read ...............................................................................................................................................225 Figure 12.9 - DMA Request Assertion Through LDRQ#.............................................................................................225 Figure 12.10 - DMA Write (First Byte) .......................................................................................................................225 Figure 12.11 - DMA Read (First Byte) ........................................................................................................................226 Figure 12.12 - X-Bus I/O Read Timing ......................................................................................................................226 Figure 12.13 - X-Bus Write Timing .............................................................................................................................227 Figure 12.14 - X-Bus and LPC I/O Read Cyle ...........................................................................................................228 Figure 12.15 - X-Bus and LPC I/O Write Cycle .........................................................................................................229 Figure 12.16 - X-Bus Memory Read...........................................................................................................................230 Figure 12.17 - X-Bus Memory Write ..........................................................................................................................231 Figure 12.18 - Microprocessor Write Timing ..............................................................................................................232 Figure 12.19 - DMA Timing ........................................................................................................................................233 Figure 12.20 - Floppy Disk Drive Timing (AT Mode Only) .........................................................................................234 Figure 12.21 - EPP 1.9 Data or Address Write Cycle.................................................................................................235 Figure 12.22 - EPP 1.9 Data or Address Read Cycle.................................................................................................236 Figure 12.23 - EPP 1.7 Data or Address Write Cycle.................................................................................................237 Figure 12.24 - EPP 1.7 Data or Address Read Cycle.................................................................................................237 Figure 12.25 - Parallel Port FIFO Timing ...................................................................................................................239 Figure 12.26 - ECP Parallel Port Forward Timing ......................................................................................................240 Figure 12.27 - ECP Parallel Port Reverse Timing ......................................................................................................241 Figure 12.28 - IrDA Receive Timing ...........................................................................................................................242 Figure 12.29 - IrDA Transmit Timing ..........................................................................................................................243 Figure 12.30 - Amplitude Shift Keyed IR Receive Timing...........................................................................................244 Figure 12.31 - Amplitude Shift Keyed IR Transmit Timing..........................................................................................245 Figure 12.32 - Setup and Hold Time ..........................................................................................................................245 Figure 12.33 - Serial Port Data...................................................................................................................................246 Figure 13.1 - XNOR-Chain Test Structure.................................................................................................................247 SMSC SIO10N268 Page 9 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet LIST OF TABLES Table 3.1 - SIO10N268 LPC Mode ..............................................................................................................................16 Table 3.2 - SIO10N268 ISA Mode................................................................................................................................17 Table 4.1 - Pin Functions .............................................................................................................................................18 Table 8.1 - Super I/O Block Addresses ........................................................................................................................34 Table 8.2 - LPC Bus Interface Signals ........................................................................................................................35 Table 8.3 - LPC Cycle Types.......................................................................................................................................35 Table 8.4 - Number of Long Syncs Inserted for Memory Cycles .................................................................................39 Table 8.5 - FWH Strapping Options .............................................................................................................................40 Table 8.6 - Description of ISA Signals..........................................................................................................................50 Table 8.7 - Status, Data and Control Registers ...........................................................................................................52 Table 8.8 - Internal 2 Drive Decode (Normal)...............................................................................................................57 Table 8.9 - Internal 2 Drive Decode (Drives 0 and 1 Swapped) ...................................................................................57 Table 8.10 - Tape Select Bits .......................................................................................................................................57 Table 8.11 - Drive Type ID ...........................................................................................................................................58 Table 8.12 - Precompensation Delays .........................................................................................................................59 Table 8.13 - Data Rates ...............................................................................................................................................59 Table 8.14 - DRVDEN Mapping0 .................................................................................................................................60 Table 8.15 - Default Precompensation Delays ............................................................................................................60 Table 8.16 - FIFO Service Delay..................................................................................................................................61 Table 8.17 - Status Register 0......................................................................................................................................64 Table 8.18 - Status Register 1......................................................................................................................................65 Table 8.19 - Status Register 2......................................................................................................................................65 Table 8.20 - Status Register 3......................................................................................................................................66 Table 8.21 - Description of Command Symbols ...........................................................................................................69 Table 8.22 - Instruction Set ..........................................................................................................................................71 Table 8.23 - Sector Sizes .............................................................................................................................................79 Table 8.24 - Effects of MT and N Bits............................................................................................................................80 Table 8.25 - Skip Bit vs Read Data command..............................................................................................................80 Table 8.26 - Skip Bit vs. Read Deleted Data Command...............................................................................................81 Table 8.27 - Result Phase Table..................................................................................................................................81 Table 8.28 - Verify Command Result Phase Table ......................................................................................................83 Table 8.29 - Typical Values for Formatting...................................................................................................................84 Table 8.30 - Interrupt Identification................................................................................................................................86 Table 8.31 - Drive Control Delays (ms) ........................................................................................................................87 Table 8.32 - Effects of WGATE and GAP Bits .............................................................................................................90 Table 8.33 - Addressing the Serial Port .......................................................................................................................91 Table 8.34 - Interrupt Control Table ..............................................................................................................................95 Table 8.35 - Baud Rates ............................................................................................................................................102 Table 8.36 - Reset Function Table ..............................................................................................................................102 Table 8.37 - Register Summary for an Individual UART Channel ..............................................................................106 Table 8.38 - FIR Transceiver Module-Type Select.....................................................................................................110 Table 8.39 - IR Rx Data Pin Selection........................................................................................................................110 Table 8.40 - Parallel Port Connector ...........................................................................................................................112 Table 8.41 - EPP Pin Descriptions ..............................................................................................................................119 Table 8.42 - ECP Pin Descriptions ..............................................................................................................................121 Table 8.43 - ECP Register Definitions .........................................................................................................................122 Table 8.44 - Mode Descriptions ..................................................................................................................................122 Table 8.45 - Extended Control Register ......................................................................................................................127 Table 8.46 - Extended Control Register (continued)..................................................................................................128 Table 8.47 - Extended Control Register (continued) ..................................................................................................128 Table 8.48 - Forward Channel Commands (HostAck Low), .......................................................................................129 Table 8.49 - Modified Parallel Port FDD Control ........................................................................................................133 Table 8.50 - FDC Parallel Port Pins ..........................................................................................................................133 Table 8.51 - PC/AT and PS/2 Available Registers .....................................................................................................137 Table 8.52 - State of Floppy Disk Drive Interface Pins in Powerdown........................................................................137 Table 8.53 - SER_IRQ Sampling Periods ..................................................................................................................140 Table 8.54 - SIO10N268 CLKRUN# Function ............................................................................................................144 Rev. 0.5 (03-24-05) Page 10 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet Table 8.55 - GPIO Pin Functionality...........................................................................................................................145 Table 8.56 - General Purpose I/O Port Assignments ................................................................................................147 Table 8.57 - GPIO Configuration Summary................................................................................................................148 Table 8.58 - GPIO Read/Write Behavior ....................................................................................................................149 Table 8.59 - PME and SMI Functionality for each GPIO ............................................................................................150 Table 9.1 - Runtime Register Block Summary ...........................................................................................................153 Table 9.2 - Runtime Registers Block Description .......................................................................................................154 Table 10.1 - Configuration Access Ports ....................................................................................................................163 Table 10.2 - Configuration Registers Summary.........................................................................................................165 Table 10.3 - CR00......................................................................................................................................................168 Table 10.4 - CR01 .....................................................................................................................................................168 Table 10.5 - CR02 .....................................................................................................................................................169 Table 10.6 - CR03......................................................................................................................................................170 Table 10.7 - CR04......................................................................................................................................................170 Table 10.8 - CR05 .....................................................................................................................................................171 Table 10.9 - DRVDEN1 Control .................................................................................................................................172 Table 10.10 - CR06....................................................................................................................................................172 Table 10.11 - CR07 ...................................................................................................................................................173 Table 10.12 - CR09....................................................................................................................................................174 Table 10.13 - CR0A ...................................................................................................................................................174 Table 10.14 - CR0B...................................................................................................................................................175 Table 10.15 - Drive Rate Table (Recommended).......................................................................................................175 Table 10.16 - CR0C ..................................................................................................................................................176 Table 10.17 - CR0F....................................................................................................................................................177 Table 10.18 - CR10 ...................................................................................................................................................177 Table 10.19 - CR11....................................................................................................................................................178 Table 10.20 - CR12....................................................................................................................................................178 Table 10.21 - CR13....................................................................................................................................................179 Table 10.22 - CR14....................................................................................................................................................179 Table 10.23 - CR15....................................................................................................................................................179 Table 10.24 - CR17....................................................................................................................................................181 Table 10.25 - CR18 ...................................................................................................................................................181 Table 10.26 - CR19 ....................................................................................................................................................182 Table 10.27 - CR1A....................................................................................................................................................183 Table 10.28 - CR1B....................................................................................................................................................183 Table 10.29 - CR1C ...................................................................................................................................................184 Table 10.30 - CR1D ...................................................................................................................................................184 Table 10.31 - UART Interrupt Operation ....................................................................................................................185 Table 10.32 - CR1E....................................................................................................................................................185 Table 10.33 - CR1F....................................................................................................................................................185 Table 10.34 - Drive Type Encoding............................................................................................................................186 Table 10.35 - CR20....................................................................................................................................................186 Table 10.36 - CR21....................................................................................................................................................187 Table 10.37 - CR22....................................................................................................................................................187 Table 10.38 - CR23....................................................................................................................................................188 Table 10.39 - Parallel Port Addressing Options .........................................................................................................188 Table 10.40 - CR24....................................................................................................................................................188 Table 10.41 - CR25....................................................................................................................................................189 Table 10.42 - CR26....................................................................................................................................................189 Table 10.43 - DMA Selection .....................................................................................................................................189 Table 10.44 - CR27....................................................................................................................................................190 Table 10.45 - IRQ Encoding ......................................................................................................................................190 Table 10.46 - CR28....................................................................................................................................................191 Table 10.47 - UART Interrupt Operation ...................................................................................................................191 Table 10.48 - CR29....................................................................................................................................................191 Table 10.49 - CR2A ...................................................................................................................................................192 Table 10.50 - CR2B ...................................................................................................................................................192 Table 10.51 - CR2C ...................................................................................................................................................193 Table 10.52 - CR2D ...................................................................................................................................................193 Table 10.53 - CR2E ...................................................................................................................................................194 SMSC SIO10N268 Page 11 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet Table 10.54 - CR2F....................................................................................................................................................194 Table 10.55 - CR30....................................................................................................................................................194 Table 10.56 - CR31 ...................................................................................................................................................195 Table 10.57 - CR32....................................................................................................................................................196 Table 10.58 - CR33....................................................................................................................................................196 Table 10.59 - CR34 ...................................................................................................................................................196 Table 10.60 - CR35....................................................................................................................................................197 Table 10.61 - CR36 ...................................................................................................................................................198 Table 10.62 - CR37 ...................................................................................................................................................198 Table 10.63 - CR38....................................................................................................................................................198 Table 10.64 - CR39....................................................................................................................................................199 Table 10.65 - CR3A ...................................................................................................................................................199 Table 10.66 - CR40 ...................................................................................................................................................200 Table 10.67 - CR41 ....................................................................................................................................................200 Table 10.68 - CR42 ...................................................................................................................................................201 Table 10.69 - CR43 ....................................................................................................................................................201 Table 10.70 - CR44 ....................................................................................................................................................202 Table 10.71 - CR45 ...................................................................................................................................................203 Table 10.72 - CR46 ....................................................................................................................................................204 Table 10.73 - CR48 ....................................................................................................................................................205 Table 10.74 - CR49 ....................................................................................................................................................206 Table 10.75 - CR4A....................................................................................................................................................206 Table 10.76 - CR4B....................................................................................................................................................207 Table 10.77 - CR4C ...................................................................................................................................................208 Table 10.78 - CR4D...................................................................................................................................................209 Table 10.79 - CR4E....................................................................................................................................................210 Table 10.80 - CR4F....................................................................................................................................................210 Table 10.81 - CR50 ....................................................................................................................................................211 Table 10.82 - CR51 ....................................................................................................................................................211 Table 10.83 - CR52 ....................................................................................................................................................212 Table 10.84 - CR53 ....................................................................................................................................................212 Table 10.85 - CR54....................................................................................................................................................213 Table 10.86 - I/O Base Address Configuration Register Description..........................................................................215 Table 10.87 - IRQ & DMA Operation in ECP Mode....................................................................................................217 Rev. 0.5 (03-24-05) Page 12 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet Chapter 1 General Description The SIO10N268 is a single chip I/O device that can be used on the ISA or LPC bus. Bus selection is accomplished as a jumper option. Offering the same part with two system busses enables easy migration from an ISA architecture to the LPC generation enabling the preservation of design techniques and BIOS. The SIO10N268 is a 3.3V operational (5.0V tolerant), PC 99/2001, and ACPI 1.0 compliant Super I/O Controller. This device includes SMSC's true CMOS 765B floppy disk controller with advanced digital data separator and SMSC's Multi-Mode parallel port with ChiProtect circuitry plus EPP and ECP support. Each variation of the part also includes 33 GPIO pins, support for two LED's with blinking option, and a WatchDog Timer (WDT) with optional output pin. The SIO10N268 includes (4) 16C550 compatible UARTs. One UART includes additional support for a Serial Infrared Interface that complies with IrDA v1.2 (Fast IR), HPSIR, and ASKIR formats, as well as Consumer IR. SIO10N268, when LPC Mode is selected, implements the LPC bus interface. In this mode, the X-Bus Interface is enabled to interface to external I/O devices that have an 8-bit data bus and to standard ISA memory devices, up to 2MB, which can serve as BIOS flash. SIO10N268, when ISA Mode is selected, supports the ISA Plug-and-Play Standard (Version 1.0a). The I/O Address, DMA Channel and Hardware IRQ of each device in the part may be reprogrammed through the internal configuration registers. SMSC SIO10N268 Page 13 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet Chapter 2 Pin Layouts The SIO10N268 may be implemented in LPC Mode or ISA Mode. The following sections show the pin layouts for each of these modes. NOTE: The mode of operation is selected by the LPC_ISA pin. The LPC_ISA pin may be connected directly to VCC to select ISA Mode (a pull-up is not recommended, but one less than 1k ohms can be used). It can either be left unconnected or connected to ground to select LPC Mode. The pin has a 30uA internal pulldown. 2.1 LPC Mode XD7 XD6 VCC XD5 XD4 XD3 XD2 XD1 XD0 XA15 XA14 XA13 XA12 XA11 XA10 XA9 XA8 XA7 XA6 VSS XA5 XA4 XA3 XA2 XA1 XA0 VCC nXWR nXRD nXCS1 nXCS0 GP57 /nDTR2 /MEMEN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 DRVDEN0 GP11 /DRVDEN1 /FDC_PP nMTR0 nDSKCHG nDS0 CLOCKI VSS nDIR nSTEP nWDATA nWGATE nHDSEL nINDEX nTRK0 nWRTPRT nRDATA CLKI32 IO_PME# VTR GP23 /nLED2 /IRQIN2 LAD0 LAD1 LAD2 LAD3 VCC LFRAME# VSS LDRQ# PCI_RESET# LPCPD# CLKRUN# PCI_CLK SIO10N268 (LPC Mode) 128 PIN TQFP GP56 /nCTS2 GP55 /nRTS2 GP54 /nDSR2 GP53 /TXD2 /IRTX GP52 /RXD2 /IRRX GP51 /nDCD2 GP50 /nRI2 nDCD1 nRI1 nDTR1 /FWHSEL nCTS1 nRTS1 /SYSOPT nDSR1 TXD1 RXD1 nSTROBE nALF nERROR nACK BUSY PE SLCT VSS PD7 PD6 PD5 VCC PD4 PD3 PD2 PD1 PD0 Rev. 0.5 (03-24-05) SER_IRQ GP30 /nRI3 GP31 /nDCD3 GP32 /RXD3 GP33 /TXD3 GP34 /nDSR3 GP35 /nRTS3 GP36 /nCTS3 GP37 /nDTR3 GP40 /nRI4 GP41 /nDCD4 GP42 /RXD4 GP43 /TXD4 GP44 /nDSR4 GP45 /nRTS4 GP46 /nCTS4 VCC GP47 /nDTR4 GP12 /IO_SMI# VSS GP13 /IRQIN1 /nLED1 LPC_ISA XA20 /GP16 XA19 /GP17 XA18 XA17 XA16 GP20 /IRRX2 /IRQIN3 GP21 /IRTX2 /WDT GP22 /IRMODE /IRRX3 /nXCS2 nINIT nSLCTIN 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Page 14 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet 2.2 ISA Mode SMSC SIO10N268 SER_IRQ GP30 /nRI3 GP31 /nDCD3 GP32 /RXD3 GP33 /TXD3 GP34 /nDSR3 GP35 /nRTS3 GP36 /nCTS3 GP37 /nDTR3 GP40 /nRI4 GP41 /nDCD4 GP42 /RXD4 GP43 /TXD4 GP44 /nDSR4 GP45 /nRTS4 GP46 /nCTS4 VCC GP47 /nDTR4 GP12 /IO_SMI# VSS GP13 /IRQIN1 /nLED1 LPC_ISA GP16 GP17 TC DRQ3 RESET_DRV GP20 /IRRX2 /IRQIN3 GP21 /IRTX2 /WDT GP22 /IRMODE /IRRX3 nINIT nSLCTIN 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 DRVDEN0 GP11 /DRVDEN1 /FDC_PP nMTR0 nDSKCHG nDS0 CLOCKI VSS nDIR nSTEP nWDATA nWGATE nHDSEL nINDEX nTRK0 nWRTPRT nRDATA CLKI32 nIO_PME VTR GP23 /nLED2 /IRQIN2 nDACK0 nDACK1 nDACK2 nDACK3 VCC DRQ0 VSS NC DRQ1 DRQ2 NC PCI_CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 SD7 SD6 VCC SD5 SD4 SD3 SD2 SD1 SD0 SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 VSS SA5 SA4 SA3 SA2 SA1 SA0 VCC nIOWR nIORD AEN IOCHRDY GP57 /nDTR2 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 SIO10N268 (ISA Mode) 128 PIN TQFP GP56 /nCTS2 GP55 /nRTS2 GP54 /nDSR2 GP53 /TXD2 /IRTX GP52 /RXD2 /IRRX GP51 /nDCD2 GP50 /nRI2 nDCD1 nRI1 nDTR1 nCTS1 nRTS1 /SYSOPT nDSR1 TXD1 RXD1 NSTROBE NALF NERROR NACK BUSY PE SLCT VSS PD7 PD6 PD5 VCC PD4 PD3 PD2 PD1 PD0 Page 15 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet Chapter 3 Pin Configurations for SIO10N268 The following tables show the pinout for the SIO10N268 in LPC Mode and ISA Mode. The mode of operation is selected by the LPC_ISA pin. The LPC_ISA pin may be connected directly to VCC to select ISA Mode (a pull-up is not recommended, but one less than 1k ohms can be used). It can either be left unconnected or connected to ground to select LPC Mode. The pin has a 30uA internal pulldown. Table 3.1 - SIO10N268 LPC Mode PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 NAME DRVDEN0 GP11 /DRVDEN1 /FDC_PP nMTR0 nDSKCHG nDS0 CLOCKI VSS nDIR nSTEP nWDATA nWGATE nHDSEL nINDEX nTRK0 nWRTPRT nRDATA CLKI32 IO_PME# VTR GP23 /nLED2 /IRQIN2 LAD0 LAD1 LAD2 LAD3 VCC LFRAME# VSS LDRQ# PCI_RESET# LPCPD# CLKRUN# PCI_CLK PIN # 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 NAME SER_IRQ GP30 /nRI3 GP31 /nDCD3 GP32 /RXD3 GP33 /TXD3 GP34 /nDSR3 GP35 /nRTS3 GP36 /nCTS3 GP37 /nDTR3 GP40 /nRI4 GP41 /nDCD4 GP42 /RXD4 GP43 /TXD4 GP44 /nDSR4 GP45 /nRTS4 GP46 /nCTS4 VCC GP47 /nDTR4 GP12 /IO_SMI# VSS GP13 /IRQIN1 /nLED1 LPC_ISA XA20 /GP16 XA19 /GP17 XA18 XA17 XA16 GP20 /IRRX2 /IRQIN3 GP21 /IRTX2 /WDT GP22 /IRMODE /IRRX3 /nXCS2 nINIT nSLCTIN PIN # 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 PD0 PD1 PD2 PD3 PD4 VCC PD5 PD6 PD7 VSS SLCT PE BUSY nACK nERROR nALF nSTROBE RXD1 TXD1 nDSR1 nRTS1 /SYSOPT nCTS1 nDTR1 /FWHSEL nRI1 nDCD1 GP50 /nRI2 GP51 /nDCD2 GP52 /RXD2 /IRRX GP53 /TXD2 /IRTX GP54 /nDSR2 GP55 /nRTS2 GP56 /nCTS2 NAME PIN # 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 NAME GP57 /nDTR2 /MEMEN nXCS0 nXCS1 nXRD nXWR VCC XA0 XA1 XA2 XA3 XA4 XA5 VSS XA6 XA7 XA8 XA9 XA10 XA11 XA12 XA13 XA14 XA15 XD0 XD1 XD2 XD3 XD4 XD5 VCC XD6 XD7 NOTE: Signals that are mode dependent are shaded gray. These signals are only available when LPC Mode is selected. Page 16 SMSC SIO10N268 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet Table 3.2 - SIO10N268 ISA Mode PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 NAME DRVDEN0 GP11 /DRVDEN1 /FDC_PP nMTR0 nDSKCHG nDS0 CLOCKI VSS nDIR nSTEP nWDATA nWGATE nHDSEL nINDEX nTRK0 nWRTPRT nRDATA CLKI32 nIO_PME VTR GP23 /nLED2 /IRQIN2 nDACK0 nDACK1 nDACK2 nDACK3 VCC DRQ0 VSS NC DRQ1 DRQ2 NC PCI_CLK PIN # 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 NAME SER_IRQ GP30 /nRI3 GP31 /nDCD3 GP32 /RXD3 GP33 /TXD3 GP34 /nDSR3 GP35 /nRTS3 GP36 /nCTS3 GP37 /nDTR3 GP40 /nRI4 GP41 /nDCD4 GP42 /RXD4 GP43 /TXD4 GP44 /nDSR4 GP45 /nRTS4 GP46 /nCTS4 VCC GP47 /nDTR4 GP12 /IO_SMI# VSS GP13 /IRQIN1 /nLED1 LPC_ISA GP16 GP17 TC DRQ3 RESET_DRV GP20 /IRRX2 /IRQIN3 GP21 /IRTX2 /WDT GP22 /IRMODE /IRRX3 nINIT nSLCTIN PIN # 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 PD0 PD1 PD2 PD3 PD4 VCC PD5 PD6 PD7 VSS SLCT PE BUSY NACK NERROR NALF NSTROBE RXD1 TXD1 nDSR1 nRTS1 /SYSOPT nCTS1 nDTR1 nRI1 nDCD1 GP50 /nRI2 GP51 /nDCD2 GP52 /RXD2 /IRRX GP53 /TXD2 /IRTX GP54 /nDSR2 GP55 /nRTS2 GP56 /nCTS2 NAME PIN # 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 NAME GP57 /nDTR2 IOCHRDY AEN nIORD nIOWR VCC SA0 SA1 SA2 SA3 SA4 SA5 VSS SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SD0 SD1 SD2 SD3 SD4 SD5 VCC SD6 SD7 NOTE: Signals that are mode dependent are shaded gray. These signals are only available when ISA Mode is selected. SMSC SIO10N268 Page 17 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet Chapter 4 Description of Pin Functions The following section describes the functionality of the pins for the SIO10N268 in LPC Mode and ISA Mode. The Mode of operation is selected by the LPC_ISA pin. The LPC_ISA pin may be connected directly to VCC to select ISA Mode (a pull-up is not recommended, but one less than 1k ohms can be used). It can either be left unconnected or connected to ground to select LPC Mode. The pin has a 30uA internal pulldown. Pins or signals that are MODE dependent are shaded gray in the following table. Table 4.1 - Pin Functions PIN # NAME FUNCTION POWER PINS (11) 25, 49, 70, 102, 126 19 7, 27, 52, 74, 109 17 6 1 2 3 4 5 8 9 10 11 12 13 14 15 16 82 VCC +3.3 Volt Supply Voltage (Note 4.10) +3.3 Volt Standby Supply Voltage (Note 4.10) Ground CLOCK PINS (2) CLKI32 CLOCKI DRVDEN0 GP11 /DRVDEN1 /FDC_PP nMTR0 nDSKCHG nDS0 nDIR nSTEP nWDATA nWGATE nHDSEL nINDEX nTRK0 nWRTPRT nRDATA RXD1 32.768kHz Standby Clock Input (Note 4.3) 14.318MHz Clock Input FDD INTERFACE (14) Drive Density Select 0 General Purpose I/O /Drive Density Select 1 /Floppy on Parallel Port Motor On 0 Disk Change Drive Select 0 Step Direction Step Pulse Write Disk Data Write Gate Head Select Index Pulse Input Track 0 Write Protected Read Disk Data SERIAL PORT 1 INTERFACE (8) Receive Data 1 IS VCC O12 IS O12 O12 O12 O12 O12 O12 IS IS IS IS IO12 O12 VCC VCC (Note 4.17) VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC IS IS VTR VCC BUFFER TYPE (Note 4.1) POWER WELL VTR VSS Rev. 0.5 (03-24-05) Page 18 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet PIN # 83 84 85 86 87 88 89 NAME TXD1 nDSR1 nRTS1 /SYSOPT nCTS1 nDTR1 /FWHSEL nRI1 nDCD1 FUNCTION Transmit Data 1 Data Set Ready 1 Request to Send 1 /(System Option) (Note 4.6) Clear to Send 1 Data Terminal Ready 1/(Firmware Hub Select) (Note 4.16) Ring Indicator 1 Data Carrier Detect 1 SERIAL PORT 2 INTERFACE (8) BUFFER TYPE (Note 4.1) O12 I OP14 I OP14 I I POWER WELL VCC VCC VCC VCC VCC VCC (Note 4.17) VCC VCC (Note 4.17) VCC 90 91 GP50 /nRI2 GP51 /nDCD2 GP52 /RXD2 /IRRX GP53 General Purpose I/O /Ring Indicator 2 General Purpose I/O /Data Carrier Detect 2 General Purpose I/O /Receive Data 2 /IRRX General Purpose I/O /Transmit Data 2 /IRTX (Note 4.8, Note 4.9) General Purpose I/O /Data Set Ready 2 General Purpose I/O /Request to Send 2 General Purpose I/O /Clear to Send 2 General Purpose I/O /Data Terminal Ready 2 /(Memory Enable Option) (Note 4.15) SERIAL PORT 3 INTERFACE (8) General Purpose I/O (Note 4.14) /Ring Indicator 3 General Purpose I/O (Note 4.14) /Data Carrier Detect 3 SERIAL PORT 3 INTERFACE (8) IO8 IO8 92 IS/O8 VCC 93 /TXD2 /IRTX IO12 VCC 94 95 96 GP54 /nDSR2 GP55 /nRTS2 GP56 /nCTS2 GP57 /nDTR2 /MEMEN GP30 /nRI3 GP31 /nDCD3 GP32 /RXD3 GP33 /TXD3 IO8 IO8 VCC VCC VCC IO8 97 IOP14 VCC 34 35 IO8 IO8 VCC (Note 4.17) VCC (Note 4.17) VCC (Note 4.17) VCC (Note 4.17) 36 37 General Purpose I/O (Note 4.14) /Receive Data 3 General Purpose I/O (Note 4.14) /Transmit Data 3 IS/O8 IO12 SMSC SIO10N268 Page 19 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet PIN # 38 39 40 41 NAME GP34 /nDSR3 GP35 /nRTS3 GP36 /nCTS3 GP37 /nDTR3 GP40 /nRI4 GP41 /nDCD4 GP42 /RXD4 GP43 /TXD4 GP44 /nDSR4 GP45 /nRTS4 GP46 /nCTS4 GP47 /nDTR4 GP20 FUNCTION General Purpose I/O (Note 4.14) /Data Set Ready 3 General Purpose I/O (Note 4.14) /Request to Send 3 General Purpose I/O (Note 4.14) /Clear to Send 3 General Purpose I/O (Note 4.14) /Data Terminal Ready 3 SERIAL PORT 4 INTERFACE (8) BUFFER TYPE (Note 4.1) IO8 IO8 IO8 IO8 POWER WELL VCC (Note 4.17) VCC (Note 4.17) VCC (Note 4.17) VCC (Note 4.17) 42 43 44 45 46 47 48 50 General Purpose I/O (Note 4.14) /Ring Indicator 4 General Purpose I/O (Note 4.14) /Data Carrier Detect 4 General Purpose I/O (Note 4.14) /Receive Data 4 General Purpose I/O (Note 4.14) /Transmit Data 4 General Purpose I/O (Note 4.14) /Data Set Ready 4 General Purpose I/O (Note 4.14) /Request to Send 4 General Purpose I/O (Note 4.14) /Clear to Send 4 General Purpose I/O (Note 4.14) /Data Terminal Ready 4 IR INTERFACE (2) General Purpose I/O /IR Receive /IRQ Input 3 General Purpose I/O (Note 4.14) /IR Transmit (Note 4.7, Note 4.9) /Watch Dog Timer IO8 IO8 IS/O8 IO12 IO8 IO8 IO8 IO8 VCC (Note 4.17) VCC VCC VCC VCC VCC VCC VCC 60 /IRRX2 /IRQIN3 GP21 IS/O8 VCC (Note 4.17) 61 /IRTX2 /WDT nINIT /nDIR nSLCTIN /nSTEP PD0 /nINDEX IO12 VCC (Note 4.17) PARALLEL PORT INTERFACE (17) (Note 4.4) 63 64 65 Initiate Output /FDC Direction Control (Note 4.5) Printer Select Input /FDC Step Pulse Port Data 0 /FDC Index OP14 OP14 IOP14/IS VCC VCC VCC Rev. 0.5 (03-24-05) Page 20 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet PIN # 66 67 68 69 71 72 73 75 76 77 78 79 80 81 NAME PD1 /nTRK0 PD2 /nWRTPRT PD3 /nRDATA PD4 /nDSKCHG PD5 PD6 /nMTR0 PD7 SLCT /nWGATE PE /nWRDATA BUSY /nMTR1 nACK /nDS1 nERROR /nHDSEL nALF /nDRVDEN0 nSTROBE /nDS0 GP12 /IO_SMI# GP13 /IRQIN1 /nLED1 GP23 Port Data 1 /FDC Track 0 Port Data 2 FUNCTION BUFFER TYPE (Note 4.1) IOP14/IS IOP14/IS IOP14/IS IOP14/IS IOP14 IOP14 /OD14 IOP14 IOD12 IOD12 IOD12 IOD12 IOD12 OP14 OP14 POWER WELL VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC /FDC Write Protected Port Data 3 /FDC Read Disk Data Port Data 4 /FDC Disk Change Port Data 5 Port Data 6 /FDC Motor On 0 Port Data 7 Printer Selected Status /FDC Write Gate Paper End /FDC Write Data Busy /FDC Motor On 1 Acknowledge /FDC Drive Select 1 Error /FDC Head Select Autofeed Output /FDC Density Select 0 (Note 4.5) Strobe Output /FDC Drive Select 0 (Note 4.5) MISCELLANEOUS GPIO PINS (3) General Purpose I/O /System Mgt. Interrupt General Purpose I/O / IRQ Input 1 /nLED1 (Note 4.11) MISCELLANEOUS GPIO PINS (3) General Purpose I/O /nLED2 (Note 4.12) /IRQ Input 2 51 IO12 VCC (Note 4.17) 53 IO12 VCC (Note 4.17) 20 /nLED2 /IRQIN2 IO12 VTR (Note 4.17) MODE INDEPENDENT INTERFACE PINS (3) 18 32 33 SMSC SIO10N268 IO_PME# PCI_CLK SER_IRQ Power Management Event Output PCI Clock (Note 4.19) Serial IRQ Page 21 OD12 PCI_ICLK PCI_IO VTR VCC VCC Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet PIN # NAME FUNCTION MODE CONTROL PIN (1) BUFFER TYPE (Note 4.1) IPD POWER WELL 54 LPC_ISA LPC or ISA device select pin (Note 4.13) MODE DEPENDENT INTERFACE PINS Multiplexed Command Address and Data 0 Multiplexed Command Address and Data 1 Multiplexed Command Address and Data 2 Multiplexed Command Address and Data 3 Frame Encoded DMA Request PCI Reset Power Down (Note 4.1) PCI Clock Controller X-BUS PINS (34) - LPC MODE ONLY X-BUS Address 20 /General Purpose I/O X-BUS Address 19 /General Purpose I/O X-BUS Address 18 X-BUS Address 17 X-BUS Address 16 General Purpose I/O (Note 4.14) /IR Mode /IR Receive 3 /X-Bus Chip Select 2 X-Bus Chip Select 0 X-BUS PINS (34) - LPC MODE ONLY VCC 21 22 23 24 26 28 29 30 31 LAD0 LAD1 LAD2 LAD3 LFRAME# LDRQ# PCI_RESET # LPCPD# CLKRUN# XA20 /GP16 XA19 /GP17 XA18 XA17 XA16 GP22 PCI_IO PCI_IO PCI_IO PCI_IO PCI_I PCI_O PCI_I PCI_I PCI_OD VCC VCC VCC VCC VCC VCC VCC VCC VCC 55 56 57 58 59 IO8 IO8 IS/O8 (Note 4.18) O8 IS/O8 (Note 4.18) VCC (Note 4.17) VCC (Note 4.17) VCC VCC VCC 62 /IRMODE /IRRX3 /nXCS2 nXCS0 IS/O8 VCC (Note 4.17) 98 O12 IO8 (Note 4.18) IO8 (Note 4.18) IO8 (Note 4.18) IO8 (Note 4.18) VCC 99 100 101 103 nXCS1 nXRD nXWR XA0 X-Bus Chip Select 1 X_BUS Read X-BUS Write X-BUS Address 0 VCC VCC VCC VCC Rev. 0.5 (03-24-05) Page 22 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet PIN # 104 105 106 107 108 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 127 128 NAME XA1 XA2 XA3 XA4 XA5 XA6 XA7 XA8 XA9 XA10 XA11 XA12 XA13 XA14 XA15 XD0 XD1 XD2 XD3 XD4 XD5 XD6 XD7 FUNCTION X-BUS Address 1 X-BUS Address 2 X-BUS Address 3 X-BUS Address 4 X-BUS Address 5 X-BUS Address 6 X-BUS Address 7 X-BUS Address 8 X-BUS Address 9 X-BUS Address 10 X-BUS Address 11 X-BUS Address 12 X-BUS Address 13 X-BUS Address 14 X-BUS Address 15 X-Bus Data Bit 0 X-Bus Data Bit 1 BUFFER TYPE (Note 4.1) IO8 (Note 4.18) IO8 (Note 4.18) IO8 (Note 4.18) IO8 (Note 4.18) IO8 (Note 4.18) IO8 (Note 4.18) IO8 (Note 4.18) IO8 (Note 4.18) IO8 (Note 4.18) IO8 (Note 4.18) IO8 (Note 4.18) IO8 (Note 4.18) IO8 (Note 4.18) IO8 (Note 4.18) IO8 (Note 4.18) IO12 IO12 IO12 IO12 IO12 IO12 IO12 IO12 POWER WELL VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC X-BUS PINS (34) - LPC MODE ONLY X-Bus Data Bit 2 X-Bus Data Bit 3 X-Bus Data Bit 4 X-Bus Data Bit 5 X-Bus Data Bit 6 X-Bus Data Bit 7 SMSC SIO10N268 Page 23 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet PIN # NAME FUNCTION BUFFER TYPE (Note 4.1) PCI_IO (Note 4.18) PCI_IO (Note 4.18) PCI_IO (Note 4.18) PCI_IO (Note 4.18) O12 O12 O12 O12 IS/O8 (Note 4.18) IS/O8 (Note 4.18) O12 (Note 4.18) IO8 (Note 4.18) IO8 (Note 4.18) IO8 (Note 4.18) IO8 (Note 4.18) IO8 (Note 4.18) IO8 (Note 4.18) IO8 (Note 4.18) IO8 (Note 4.18) IO8 (Note 4.18) POWER WELL ISA INTERFACE (38) - ISA MODE ONLY 21 22 23 24 26 29 30 58 57 59 98 99 100 101 103 104 105 106 nDACK0 nDACK1 nDACK2 nDACK3 DRQ0 DRQ1 DRQ2 DRQ3 TC RESET_DRV IOCHRDY AEN nIORD nIOWR SA0 SA1 SA2 SA3 DMA Acknowledge 0 DMA Acknowledge 1 DMA Acknowledge 2 DMA Acknowledge 3 DMA Request 0 DMA Request 1 DMA Request 2 DMA Request 3 Terminal Count ISA Reset Drive I/O Channel Ready Address Enable I/O Read I/O Write System Address Bus System Address Bus System Address Bus System Address Bus VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC ISA INTERFACE (38) - ISA MODE ONLY 107 108 SA4 SA5 System Address Bus System Address Bus VCC VCC Rev. 0.5 (03-24-05) Page 24 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet PIN # 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 127 128 55 56 62 NAME SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 GP16 GP17 GP22 /IRMODE /IRRX3 FUNCTION System Address Bus System Address Bus System Address Bus System Address Bus System Address Bus System Address Bus System Address Bus System Address Bus System Address Bus System Address Bus System Data Bus System Data Bus System Data Bus System Data Bus System Data Bus System Data Bus System Data Bus System Data Bus General Purpose I/O General Purpose I/O General Purpose I/O (Note 4.14) /IR Mode /IR Receive 3 BUFFER TYPE (Note 4.1) IO8 (Note 4.18) IO8 (Note 4.18) IO8 (Note 4.18) IO8 (Note 4.18) IO8 (Note 4.18) IO8 (Note 4.18) IO8 (Note 4.18) IO8 (Note 4.18) IO8 (Note 4.18) IO8 (Note 4.18) IO12 IO12 IO12 IO12 IO12 IO12 IO12 IO12 IO8 IO8 IS/O8 POWER WELL VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VTR (Note 4.17) VCC VCC (Note 4.17) MISCELLANEOUS MODE DEPENDENT PINS (3) - ISA MODE ONLY NOTE: The "n" as the first letter of a signal name or the "#" as the suffix of a signal name indicates an "Active Low" signal. Pins that have input buffers must always be held to either a logical low or a logical high state when powered. Bi-directional buses that may be tristated should have either weak external pull-ups or pulldowns to prevent the pins from floating. Note 4.1 SMSC SIO10N268 Page 25 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet Note 4.2 The LPCPD# pin may be tied high. The LPC interface will function properly if the PCI_RESET# signal follows the protocol defined for the LRESET# signal in the "Low Pin Count Interface Specification". If the 32kHz input clock is not used the CLKI32 pin must be grounded. There is a bit in the configuration register at CR1E that determines whether the 32KHz clock input is used as the clock source for the WDT and the LED's. Set this bit to `1' if the clock is not connected. The FDD output pins multiplexed in the PARALLEL PORT INTERFACE are OD drivers only and are not affected by the FDD Output Driver Controls (see subsection CR05 in the Configuration section). Active (push-pull) output drivers are required on these pins in the enhanced parallel port modes. The nRTS1/SYSOPT pin requires an external pulldown resistor to put the base I/O address for configuration at 0x02E. An external pullup resistor is required to move the base I/O address for configuration to 0x04E. The GP21/IRTX2/WDT pin is tristate when VCC=0. The pin comes up as an output and low following a VCC POR and Hard Reset if configured for IRTX2 function. The GP21/IRTX2/WDT pin will remain low following a power-up (VCC POR) if configured for IRTX2 until serial port 2 is enabled by setting the UART2 Power bit to `1'. Once the power has been applied the pin will reflect the state of the IR transmit output of the IRCC block. If this pin is configured for GPIO function, the pin will reflect the state of the GPIO on a VCC POR. The GP53/TXD2/IRTX pin defaults to tristate when the part is under VTR power (VCC=0). The pin comes up tristate following a VTR POR, VCC POR, and Hard Reset. If the pin is configured for alternate functions TXD2 or IRTX the GP53/TXD2/IRTX pin will remain tristate following a power-up (VCC POR) until the UART2 Power bit is set to `1'. Once the power has been applied to the UART, the pin will reflect the current state of the output transmit buffer. If this pin is configured for GPIO function, the pin will reflect the state of the GPIO on a VCC POR. VTR can be connected to VCC if no wakeup functionality is required. VCC must not be greater than 0.5V above VTR. The nLED1 pin is powered by VCC and can only be controlled when the part is under VCC power. The nLED2 pin is powered by VTR so that the LED can be controlled when the part is under VTR power. The LPC_ISA pin may be connected directly to VCC to select ISA Mode (a pull-up is not recommended, but one less than 1k ohms can be used). It can either be left unconnected or connected to ground to select LPC Mode. The pin has a 30uA internal pulldown. These GPIO pins only have push-pull buffers. They cannot be configured for open drain outputs. MEMEN is a strapping option to enable/disable memory decoding on the LPC interface for the X-Bus. When MEMEN is asserted (high), the LPC interface will decode memory or FWH addresses for the XBus. When MEMEN is deasserted (low), the LPC interface will not decode memory or FWH addresses FWHSEL is a strapping option to determine the type of memory cycle decoded when the MEMEN strapping option is asserted. Assuming X-Bus memory cycles are enabled (MEMEN = 1), when FWHSEL is asserted (high) FWH memory cycles are decoded for the X-Bus. When FWHSEL is deasserted (low), LPC memory cycles are decoded for the X-Bus. If MEMEN=0, FWHSEL is has no effect (i.e., Don't Care). These pins have input buffers into the wakeup logic that are powered by VTR. Note 4.3 Note 4.4 Note 4.5 Note 4.6 Note 4.7 Note 4.8 Note 4.9 Note 4.10 Note 4.11 Note 4.12 Note 4.13 Note 4.14 Note 4.15 Note 4.16 Note 4.17 Rev. 0.5 (03-24-05) Page 26 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet Note 4.18 This buffer type is different from the buffer types shown per function because it is a mode dependent pin that supports alternate `mode dependent' functions that require additional buffer types. The PCI Clock is considered part of the LPC Interface when the device is configured for LPC Mode and it is also considered part of the ISA Interface when the device is configured for ISA Mode. In LPC Mode, the PCI Clock must always be driven by the 33MHz PCI Clock source. In ISA Mode, the PCI Clock is used to support serial IRQs. If serial IRQs are not supported then the PCI Clock input may be connected to the 33MHz PCI Clock or the 14MHz clock source. Note 4.19 SMSC SIO10N268 Page 27 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet 4.1 I IS IPD O6 O8 OD8 IO8 O12 OD12 IO12 OD14 OP14 IOP14 PCI_I PCI_O PCI_OD PCI_IO PCI_ICLK Note 4.20 Note 4.21 Buffer Type Description Input TTL Compatible. Input with Schmitt Trigger. Input with 30uA Integrated Pull-Down Output, 6mA sink, 3mA source. Output, 8mA sink, 4mA source. Open Drain Output, 8mA sink. Input/Output, 8mA sink, 4mA source. Output, 12mA sink, 6mA source. Open Drain Output, 12mA sink. Input/Output, 12mA sink, 6mA source. Open Drain Output, 14mA sink. Output, 14mA sink, 14mA source. Input/Output, 14mA sink, 14mA source. Backdrive protected. Input. These pins meet the PCI 3.3V AC and DC Characteristics. (Note 4.20) Output. These pins meet the PCI 3.3V AC and DC Characteristics. (Note 4.20) Open Drain Output. These pins meet the PCI 3.3V AC and DC Characteristics. (Note 4.20) Input/Output. These pins meet the PCI 3.3V AC and DC Characteristics. (Note 4.20) Clock Input. These pins meet the PCI 3.3V AC and DC Characteristics and timing. (Note 4.21) See the PCI Local Bus Specification, Revision 2.1, Section 4.2.2. See the PCI Local Bus Specification, Revision 2.1, Section 4.2.2. and 4.2.3. 4.2 Design Guidelines for Implemented Buffer Types The characteristics of the I/O buffers implemented in this device are defined in section 11.2 DC Electrical Characteristics on page 218. Care should be taken to ensure that external devices maintain acceptable voltage levels on all inputs and open drain outputs. It is not advisable to allow input buffers to float or remain in an indeterminate state. NOTE: It is important not to cross power domains when attaching pull-ups to pins. Pins that are located on the VCC power well must be pulled either to ground or to VCC. This includes GPIO pins with wakeup capability that are located on the VCC power well (see Table 4.1 - Pin Functions on page 18). Pins that are located on the VTR power well must be pulled either to ground or to VTR. The following is a list of design guidelines to help identify which pins require external pull-up/pull-down resistors: 1) Input buffers that are of type I or IS must be driven to a logic high or a logic low when power is applied to the buffer. If the external device controlling the input buffer tristates while power is applied to the buffer, an external pull-up/pull-down resistor should be added to prevent the pin from floating. All output pins that are implemented as open drain outputs, must be pulled through an external resistor to the proper VCC or VTR power plane. All GPIO registers default to a GPIO input on a VTR POR. On a cold boot, a VCC POR will implement these pins as GPIO inputs. It is suggested that these pins are pulled to their inactive state (either to the proper VCC or VTR power plane or ground) depending on the function being implemented on the pin. Bi-directional buffers that change direction as part of their functionality require either pull-ups or pulldowns to prevent the input buffer from floating when the bus is tristated. The SIO10N268 has bidirectional data busses that require external resistors pulled to a logic high or a logic low. They are the parallel data pins (PD[0:7]), the X-Bus data pins (XD[0:7]) - LPC Mode only, and ISA data pins (SD[0:7]) - ISA Mode only) 2) 3) 4) Rev. 0.5 (03-24-05) Page 28 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet Chapter 5 Block Diagram LPC_ISA nIO_SMI* nIO_PME PD[0:7], DRQ0 nDACK0 DRQ1 nDACK1 DRQ2 nDACK2 DRQ3 nDACK3 TC RESET_DRV IOCHRDY AEN nIORD nIOWR SA[0:15] SD[0:7] XD[0:7] nXCS0 nXCS1 nXCS2* nXRD nXWR XA[0:18] XA[19:20]* LAD0 LAD1 LAD2 LAD3 LFRAME# LDRQ# PCI_RESET# LPCPD# CLKRUN# SER_IRQ PCI_CLK SMI PME MULTIMODE PARALLEL PORT/FDC MUX BUSY, SLCT, PE, nERROR, nACK nSLCTIN, nALF nINIT, nSTROBE GP[11:13]*, GP[16:17]*, GP[20:23]*, GP[30:37]*, GP[40:47]*, GP[50:57]* IRQIN1*, IRQIN2*, IRQIN3* FDC_PP* ISA Interface CONTROL, ADDRESS, DATA GENERAL PURPOSE I/O CONFIGURATION REGISTERS LED Driver LED1*, LED2* X-BUS INTERFACE LPC_IS A Mode Select ACPI BLOCK Watch Dog Timer WDT* SIO10N268 LPC BUS INTERFACE 16C550 COMPATIBLE SERIAL PORT 1 TXD1, nRTS1, nDTR1 nCTS1, RXD1, nDSR1, nDCD1, nRI1 16C550 COMPATIBLE SERIAL PORT 2 WITH INFRARED INTERFACE 16C550 COMPATIBLE SERIAL PORT 3 SMSC PROPRIETARY 82077 COMPATIBLE VERTICAL FLOPPY DISK CONTROLLER CORE WDATA WCLOCK DIGITAL DATA SEPERATOR PRERCLOCK COMPENSATION RDATA 16C550 COMPATIBLE SERIAL PORT 4 IRTX2*, IRMODE*, TXD2*, nRTS2*, nDTR2* IRRX2*, IRRX3*, RXD2*, nCTS2*, nDSR2*, nDCD2*, nRI2* Serial IRQ TXD3*, nRTS3,* nDTR3* nCTS3*, RXD3*, nDSR3*, nDCD3*, nRI3* CLOCK GEN TXD4*, nRTS4*, nDTR4* nCTS4*, RXD*, nDSR4*, nDCD*, nRI4* CLKI32 CLOCKI V Vcc Vss TR nMTR0, nDS0, nDIR, nSTEP, DRVDEN0, nWGATE, HDSEL, DRVDEN1* nTRK0, nDSKCHG, nINDEX, nWRTPRT nWDATA nRDATA * Denotes Multifunction Pins Figure 5.1 - SIO10N268 Block Diagram SMSC SIO10N268 Page 29 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet Chapter 6 3.3 Volt Operation / 5 Volt Tolerance The SIO10N268 is a 3.3 Volt part. It is intended solely for 3.3V applications. Non-LPC bus pins are 5V tolerant; that is, the input voltage is 5.5V max, and the I/O buffer output pads are backdrive protected. The LPC interface pins are 3.3 V only. These signals meet PCI DC specifications for 3.3V signaling. These pins are: LAD[3:0] LFRAME# LDRQ# LPCPD# The input voltage for all other pins is 5.5V max. These pins include all non-LPC Bus pins and the following pins: PCI_RESET# PCI_CLK SER_IRQ CLKRUN# IO_PME# Rev. 0.5 (03-24-05) Page 30 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet Chapter 7 Power Functionality The SIO10N268 has two power planes: VCC and VTR. 7.1 VCC Power The SIO10N268 is a 3.3 Volt part. The VCC supply is 3.3 Volts (nominal). Description Section and the Maximum Current Values subsection. See the Operational 7.2 VTR Support The SIO10N268 requires a trickle supply (VTR) to provide sleep current for the programmable wake-up events in the PME interface when VCC is removed. The VTR supply is 3.3 Volts (nominal). See the Operational Description Section. The maximum VTR current that is required depends on the functions that are used in the part. See Trickle Power Functionality subsection and the Maximum Current Values subsection. If the SIO10N268 is not intended to provide wake-up capabilities on standby current, VTR can be connected to VCC. The VTR pin generates a VTR Power-on-Reset signal to initialize these components. NOTE: If VTR is to be used for programmable wake-up events when VCC is removed, VTR must be at its full minimum potential at least 10 s before VCC begins a power-on cycle. When VTR and VCC are fully powered, the potential difference between the two supplies must not exceed 500mV. 7.3 32.768 kHz Trickle Clock Input The SIO10N268 utilizes a 32.768 kHz trickle input to supply a clock signal for the Watchdog Timer (WDT) and LED blink function. NOTE: LED1 has a VCC powered output pin and will only generate a signal when the device is powered by VCC. LED2 has a VTR powered output pin and may be used under VTR power. The SIO10N268 has two different methods of deriving a 32.768kHz signal: From an external single-input clock source driven on the CLKI32 pin From an internal PLL that divides down the14MHz clock input to make the 32kHz signal If the 32kHz input clock is not used the CLKI32 pin must be grounded and the CLK32_PRSN bit should be set to `1'. This bit in the configuration register block at register index CR1E determines whether the internal 32KHz clock is derived from the CLKI32 pin or the 14MHz clock input. This clock input is used as the clock source for the WDT and the LEDs. This register is powered by VTR and reset on a VTR POR. Bit[0] (CLK32_PRSN) is defined as follows: 0=32kHz clock is connected to the CLKI32 pin (default) 1=32kHz clock is not connected to the CLKI32 pin (pin is grounded). Bit 0 controls the source of the 32kHz (nominal) clock for the LED blink logic and the WDT. When the external 32kHz clock is connected, bit[0] should be set to `0' so that the external clock will be the source for the LED blink logic and the WDT. When the external 32kHz clock is not connected, bit[0] should be set to `1' so that an internal 32kHz clock source will be derived from the 14MHz clock for the LED blink logic and the WDT. SMSC SIO10N268 Page 31 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet The following functions will not work under VTR power (VCC removed) if the external 32kHz clock is not connected. These functions will work under VCC power even if the external 32kHz clock is not connected. LED blink WDT 7.4 Internal PWRGOOD An internal PWRGOOD logical control is included to minimize the effects of pin-state uncertainty in the host interface as VCC cycles on and off. When the internal PWRGOOD signal is "1" (active), VCC > 2.3V (nominal), and the SIO10N268 host interface is active. When the internal PWRGOOD signal is "0" (inactive), VCC 2.3V (nominal), and the SIO10N268 host interface is inactive; that is, LPC bus reads and writes will not be decoded. The SIO10N268 device pins IO_PME#, nRI1, nRI2, nRI3, nRI4, and most GPIOs (as input) are part of the PME interface and remain active when the internal PWRGOOD signal has gone inactive, provided VTR is powered. See Trickle Power Functionality section. 7.5 Trickle Power Functionality When the SIO10N268 is running under VTR only, the PME wakeup events are active and (if enabled) able to assert the IO_PME# pin active low. The following lists the wakeup events: UART 1 Ring Indicator UART 2 Ring Indicator UART 3 Ring Indicator UART 4 Ring Indicator WDT GPIOs for wakeup. See below. The following requirements apply to all I/O pins that are specified to be 5 volt tolerant. I/O buffers that are wake-up event compatible are powered by VCC. Under VTR power (VCC=0), these pins may only be configured as inputs. These pins have input buffers into the wakeup logic that are powered by VTR. I/O buffers that may be configured as either push-pull or open drain under VTR power (VCC=0), are powered by VTR. This means they will, at a minimum, source their specified current from VTR even when VCC is present. The GPIOs that are used for PME wakeup inputs are GP11-GP13, GP16-GP17, GP20-GP23, GP30GP37, GP40, and GP50. These GPIOs function as follows: Buffers are powered by VCC, but in the absence of VCC they are backdrive protected (they do not impose a load on any external VTR powered circuitry). They are wakeup compatible as inputs under VTR power. These pins have input buffers into the wakeup logic that are powered by VTR. All GPIOs listed above are for PME wakeup as a GPIO function (or alternate function). See the Table in the GPIO section for more information. The following list summarizes the blocks, registers and pins that are powered by VTR. PME interface block CLKI32 WDT block Rev. 0.5 (03-24-05) Page 32 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet LED block LED2 pin Runtime register block (includes all PME, SMI, WDT, LED, and GP data registers) Pins for PME Wakeup: - GPIOs (GP11-GP13, GP16-GP17, GP20-GP23, GP30-GP37, GP40, and GP50) - IO_PME# - nRI1, nRI2, nRI3, nRI4 7.6 Maximum Current Values See Chapter 11 Operational Description for the maximum current values. The maximum VTR current, ITR, is given with all outputs open (not loaded), and all inputs in a fixed state (i.e., 0V or 3.3V). The total maximum current for the part is the unloaded value PLUS the maximum current sourced by the pin that is driven by VTR. The pins that are powered by VTR (as output) are IO_PME#, LED2 and nPME. These pins, if configured as a push-pull output, will source a minimum of 6mA at 2.4V when driving. The maximum VCC current, ICC, is given with all outputs open (not loaded), and all inputs in a fixed state (i.e., 0V or 3.3V). 7.7 Power Management Events (PME/SCI) The SIO10N268 offers support for Power Management Events (PMEs), also referred to as System Control Interrupt (SCI) events. The terms PME and SCI are used synonymously throughout this document to refer to the indication of an event to the chipset via the assertion of the nIO_PME output signal on pin 18. See the "PME Support" section. SMSC SIO10N268 Page 33 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet Chapter 8 8.1 Functional Description Super I/O Registers The address map, shown below in Table 8.1, shows the addresses of the different blocks of the Super I/O immediately after power up. The base addresses of the FDC, serial and parallel ports, runtime register block and configuration register block can be moved via the configuration registers. Some addresses are used to access more than one register. 8.2 Host Processor Interface (LPC or ISA) The host processor interface is selectable by the LPC_ISA pin (pin 54). The LPC_ISA pin may be connected directly to VCC to select ISA mode (a pull-up is not recommended, but one less than 1k ohms can be used). It can either be left unconnected or connected to ground to select LPC Mode. Mode dependent interface pins are shown in the table located in section Chapter 4 Description of Pin Functions on page 18. The host processor communicates with the SIO10N268 through a series of read/write registers via the host processor interface (LPC or ISA). The port addresses for these registers are shown in Table 8.1. Register access is accomplished through I/O cycles or DMA transfers. All registers are 8 bits wide. Table 8.1 - Super I/O Block Addresses ADDRESS Base+(0-5) and +(7) Base+(0-7) Base1+(0-7) Base2+(0-7) Base+(0-7) Base+(0-7) Base+(0-3) Base+(0-7) Base+(0-3), +(400-402) Base+(0-7), +(400-402) Base + (0-F) Base + (0-1) Base +(0) Base +(0) Note 8.1 BLOCK NAME Floppy Disk Serial Port Com 1 Serial Port Com 2 Serial Port Com 3 Serial Port Com 4 Parallel Port SPP EPP ECP ECP+EPP+SPP Runtime Registers Configuration X-Bus Chip Select 1 (nXCS1) Chip Select 2 (nXCS2) NOTES IR Support FIR and CIR Refer to the configuration register descriptions for setting the base address. Rev. 0.5 (03-24-05) Page 34 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet 8.3 LPC Interface (LPC Mode only) LPC Mode is enabled if the LPC_ISA pin (pin 54) is left unconnected of if it is connected to ground. The SIO10N268 communicates with the host over a Low Pin Count (LPC) interface. For a complete description of the LPC interface, see the Intel Low Pin Count Specification, Rev 1.0. The following sections define the LPC signals implemented, the cycles supported, and protocols implemented that are specific to this device. NOTE: The LPC interface uses 3.3V signaling. For electrical specifications see the Intel Low Pin Count Specification, Rev 1.0 and the PCI Local Bus Specification, Rev 2.2. 8.3.1 LPC Interface Signal Definition The signals required for the LPC bus interface are described in the table below. LPC bus signals use PCI 33MHz electrical signal characteristics. Table 8.2 - LPC Bus Interface Signals SIGNAL NAME LAD[3:0] LFRAME# PCI_RESET# LDRQ# IO_PME# LPCPD# PCI_CLK CLKRUN# IO_SMI# Note 8.2 TYPE I/O Input Input Output OD Input Input I/OD OD DESCRIPTION LPC address/data bus. Multiplexed command, address and data bus. Frame signal. Indicates start of new cycle and termination of broken cycle PCI Reset. Used as LPC Interface Reset. Encoded DMA/Bus Master request for the LPC interface. Power Mgt Event signal. Allows the SIO10N268 to request wakeup. Powerdown Signal. Indicates that the SIO10N268 should prepare for power to be shut on the LPC interface. PCI Clock. Clock Run. Allows the SIO10N268 to request the stopped PCI_CLK be started. System Mgt Interrupt signal. Allows the SIO10N268 to notify the host system that an event has occurred. The IO_PME#, IO_SMI#, and PCI_CLK signals are considered part of the host interface. They are available in both LPC Mode and ISA Mode. 8.3.2 LPC Cycles Table 8.3 - LPC Cycle Types CYCLE TYPE (Note 8.3) TRANSFER SIZE 1 Byte 1 Byte 1 Byte 1 Byte 1 Byte (Note 8.4, Note 8.5) 1 Byte (Note 8.4, Note 8.5) The following cycle types are supported by the LPC protocol. I/O Write I/O Read DMA Write DMA Read Memory Read Memory Write Note 8.3 Note 8.4 The SIO10N268 ignores cycles that it does not support. LPC memory is only supported within the FWH ranges specified in section 8.4.2 FWH and LPC Memory Addressing on page 41. Page 35 Rev. 0.5 (03-24-05) SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet Note 8.5 LPC Memory transactions are only enabled if the MEM_EN bit is set to `1' and the FWH_SEL bit is set to `0' in the FWH ID Select register. 8.3.3 LFRAME# Usage LFRAME# is used by the host to indicate the start of cycles and the termination of cycles due to an abort or time-out condition. This signal is to be used by the SIO10N268 to know when to monitor the bus for a cycle. This signal is used as a general notification that the LAD[3:0] lines contain information relative to the start or stop of a cycle, and that the SIO10N268 monitors the bus to determine whether the cycle is intended for it. The use of LFRAME# allows the SIO10N268 to enter a lower power state internally. There is no need for the SIO10N268 to monitor the bus when it is inactive, so it can decouple its state machines from the bus, and internally gate its clocks. When the SIO10N268 samples LFRAME# active, it immediately stops driving the LAD[3:0] signal lines on the next clock and monitor the bus for new cycle information. The LFRAME# signal functions as described in the Low Pin Count (LPC) Interface Specification Revision 1.0. 8.3.4 Field Definitions LPC transactions are defined as being comprised of multiple fields. These fields may be one or more nibbles in length (nibble=4 bits). All LPC transactions begin with a START field and a Cycle Type/Direction field. The START field is used to initiate/terminate LPC transactions. The Cycle Type/Direction field is used to define the cycle type (memory, I/O, DMA) and direction (read/write) for LPC cycles. The remaining fields of data being transfered are based on specific fields that are used in various combinations, depending on the cycle type. These remaining fields are driven on to the LAD[3:0] signal lines to communicate address, control and data information over the LPC bus between the host and the SIO10N268. See the Low Pin Count (LPC) Interface Specification Revision 1.0 from Intel, Section 4.2 for definition of these fields. The following sections describe the supported cycle types. NOTE: I/O, DMA, and Memory cycles use a START field of 0000. 8.3.4.1 I/O Read and Write Cycles The SIO10N268 is the target for I/O cycles. I/O cycles are initiated by the host for register or FIFO accesses, and will generally have minimal Sync times. The minimum number of wait-states between bytes is 1. EPP cycles will depend on the speed of the external device, and may have much longer Sync times. Data transfers are assumed to be exactly 1-byte. If the CPU requested a 16 or 32-bit transfer, the host will break it up into 8-bit transfers. See the Low Pin Count (LPC) Interface Specification Reference, Section 5.2, for the sequence of cycles for the I/O Read and Write cycles. 8.3.4.2 DMA Read and Write Cycles DMA read cycles involve the transfer of data from the host (main memory) to the SIO10N268. DMA write cycles involve the transfer of data from the SIO10N268 to the host (main memory). Data will be coming from or going to a FIFO and will have minimal Sync times. Data transfers to/from the SIO10N268 are 1 byte. Rev. 0.5 (03-24-05) Page 36 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet See the Low Pin Count (LPC) Interface Specification Reference, Section 6.4, for the field definitions and the sequence of the DMA Read and Write cycles. DMA Protocol DMA on the LPC bus is handled through the use of the LDRQ# lines from the SIO10N268 and special encodings on LAD[3:0] from the host. The DMA mechanism for the LPC bus is described in the Low Pin Count (LPC) Specification Revision 1.0. 8.3.4.3 Memory Read and Write Cycles If enabled, the LPC interface is capable of decoding memory cycles that are located in the FWH address ranges specified in section 8.4.2 FWH and LPC Memory Addressing on page 41. To enable LPC memory decoding the MEM_EN bit must be set to `1' and the FWH_SEL bit must be set to `0' in the FWH ID Select register located at offset CR54. The value of these bits is determined on a VCC POR and Hard Reset by the value of the MEM_EN and FWH_SEL strapping options. When VCC>2.4V the MEM_EN and FWH_SEL bits located in the FWH_ID select register can be modified by software. See Table 8.5 - FWH Strapping Options for a description of these strapping options. For a description of the LPC memory read/write cycles refer to section 5.1 Memory Cycles of the LPC Specification. 8.3.5 8.3.5.1 Power Management CLOCKRUN Protocol See the Low Pin Count (LPC) Interface Specification Reference, Section 8.1. 8.3.5.2 LPCPD Protocol The SIO10N268 will function properly if the LPCPD# signal goes active and then inactive again without PCI_RESET# becoming active. This is a requirement for notebook power management functions. Although the LPC Bus spec 1.0 section 8.2 states, "After LPCPD# goes back inactive, the LPC I/F will always be reset using LRST#", this statement does not apply for mobile systems. LRST# (PCI_RESET#) will not occur if the LPC Bus power was not removed. For example, when exiting a "light" sleep state (ACPI S1, APM POS), LRST# (PCI_RESET#) will not occur. When exiting a "deeper" sleep state (ACPI S3-S5, APM STR, STD, soft-off), LRST# (PCI_RESET#) will occur. The LPCPD# pin is implemented as a "local" powergood for the LPC bus in the SIO10N268. It is not used as a global powergood for the chip. It is used to reset the LPC block and hold it in reset. An internal powergood is implemented in SIO10N268 to minimize power dissipation in the entire chip. Prior to going to a low-power state, the system will assert the LPCPD# signal. It will go active at least 30 microseconds prior to the LCLK# (PCI_CLK) signal stopping low and power being shut to the other LPC I/F signals. Upon recognizing LPCPD# active, the SIO10N268 will drive the LDRQ# signal low or tri-state, and do so until LPCPD# goes back active. Upon recognizing LPCPD# inactive, the SIO10N268 will drive its LDRQ# signal high. SMSC SIO10N268 Page 37 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet See the Low Pin Count (LPC) Interface Specification Reference, Section 8.2. 8.3.5.3 SYNC Protocol See the Low Pin Count (LPC) Interface Specification Reference, Section 4.2.1.8 for a table of valid SYNC values. The SYNC pattern is used to add wait states. For read cycles, the SIO10N268 immediately drives the SYNC pattern upon recognizing the cycle. The host immediately drives the sync pattern for write cycles. If the SIO10N268 needs to assert wait states, it does so by driving 0101 or 0110 on LAD[3:0] until it is ready, at which point it will drive 0000 or 1001. The SIO10N268 will choose to assert 0101 or 0110, but not switch between the two patterns. The data (or wait state SYNC) will immediately follow the 0000 or 1001 value. The SYNC value of 0101 is intended to be used for normal wait states, wherein the cycle will complete within a few clocks. The SIO10N268 uses a SYNC of 0101 for all wait states in a DMA transfer. The SYNC value of 0110 is intended to be used where the number of wait states is large. This is provided for EPP cycles, where the number of wait states could be quite large (>1 microsecond). However, the SIO10N268 uses a SYNC of 0110 for all wait states in an I/O transfer. The SYNC value is driven within 3 clocks. 8.3.5.4 SYNC Timeout The SYNC value is driven within 3 clocks. If the host observes 3 consecutive clocks without a valid SYNC pattern, it will abort the cycle. The SIO10N268 does not assume any particular timeout. When the host is driving SYNC, it may have to insert a very large number of wait states, depending on PCI latencies and retries. 8.3.5.5 SYNC Patterns and Maximum Number of SYNCS If the SYNC pattern is 0101, then the host assumes that the maximum number of SYNCs is 8. If the SYNC pattern is 0110, then no maximum number of SYNCs is assumed. The SIO10N268 has protection mechanisms to complete the cycle. This is used for EPP data transfers and will utilize the same timeout protection that is in EPP. 8.3.5.6 SYNC Error Indication The SIO10N268 reports errors via the LAD[3:0] = 1010 SYNC encoding. If the host was reading data from the SIO10N268, data will still be transferred in the next two nibbles. This data may be invalid, but it will be transferred by the SIO10N268. If the host was writing data to the SIO10N268, the data had already been transferred. In the case of multiple byte cycles, such as DMA cycles, an error SYNC terminates the cycle. Therefore, if the host is transferring 4 bytes from a device, if the device returns the error SYNC in the first byte, the other three bytes will not be transferred. Rev. 0.5 (03-24-05) Page 38 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet 8.3.5.7 Reset Policy The following rules govern the reset policy: 1) When PCI_RESET# goes inactive (high), the clock is assumed to have been running for 100usec prior to the removal of the reset signal, so that everything is stable. This is the same reset active time after clock is stable that is used for the PCI bus. When PCI_RESET# goes active (low): a) b) the host drives the LFRAME# signal high, tristates the LAD[3:0] signals, and ignores the LDRQ# signal. the SIO10N268 ignores LFRAME#, tristate the LAD[3:0] pins and drive the LDRQ# signal inactive (high). 2) 8.3.6 8.3.6.1 LPC Transfers Wait State Requirements I/O Transfers For I/O transfers in which long indeterminate wait states are required (i.e., EPP or IrCC transfers) the sync pattern of 0110 is used and a large number of syncs may be inserted (up to 330 which corresponds to a timeout of 10us). NOTE: Wait states are required for all I/O transfers. Three wait states are required for an I/O read and two wait states are required for an I/O write. A SYNC of 0110 is used for all I/O transfers. DMA Transfers The SIO10N268 inserts three wait states for a DMA read and four wait states for a DMA write cycle. A SYNC of 0101 is used for all DMA transfers. Memory Transfers For FWH or LPC memory cycles initiated on the LPC interface the number of syncs inserted is dependent on the read/write pulse width programmed for the X-Bus interface. The pulse width is programmed via the CR53 X-Bus chip Select 0 Register which can be found on page 212. The following table summarizes the number of Long Sync (6\H) clock cycles for LPC and FWH memory transactions. Table 8.4 - Number of Long Syncs Inserted for Memory Cycles MIN PULSE WIDTH 150 ns 120 ns 90 ns 60 ns Note 8.6 LPC MEMORY READ 11 10 9 8 LPC MEMORY WRITE 7 6 5 4 FWH READ 11 10 9 8 FWH WRITE 0 0 0 0 Long sync cycles are always followed by one ready sync cycle (0\H). See the example timing for the LPC cycles in Chapter 12 Timing Diagrams. SMSC SIO10N268 Page 39 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet 8.4 FWH Interface (LPC Mode Only) The Firmware Hub (FWH) interface shares the LPC interface pins LAD[3:0] and LFRAME#. The FWH implements a specific memory cycle for the purpose of interface for the BIOS. If enabled, the FWH cycles in the SIO10N268 are forwarded to the X-Bus Interface. To enable FWH memory cycle decoding the MEM_EN bit must be set to `1' and the FWH_SEL bit must be set to `1' in the FWH ID Select register located at offset CR54. The default value of these bits is determined by the MEM_EN and FWH_SEL strapping options. (See Table 8.5 - FWH Strapping Options) The FWH supports single byte memory transactions only. 8.4.1 Enabling the FWH Interface The LPC interface can be used to decode FWH memory cycles if enabled. To enable FWH memory cycle decoding the MEM_EN bit must be set to `1' and the FWH_SEL bit must be set to `1' in the FWH ID Select register located at offset CR54. The default value of these bits is determined by the MEM_EN and FWH_SEL strapping options. The following table defines the FWH Strapping options. Table 8.5 - FWH Strapping Options 1. NAME MEMEN OPTIONS 1 = X-Bus Memory Cycles Enabled 0 = X-Bus Memory Cycles Disabled PIN GP57/nDTR2 DESCRIPTION When MEMEN is asserted, the LPC interface will decode memory or FWH addresses for the X-Bus. When MEMEN is deasserted, the LPC interface will not decode memory or FWH addresses Assuming X-Bus memory cycles are enabled (MEMEN = 1), when FWHSEL is asserted FWH memory cycles are decoded for the X-Bus. When FWHSEL is deasserted, LPC memory cycles are decoded for the XBus. 2. FWHSEL 1 = FWH Memory Cycles Selected 0 = LPC Memory Cycles Selected nDTR1 8.4.1.1 MEMEN The MEMEN strap option determines if memory cycles are decoded for the X-Bus interface. When the MEMEN strap option is asserted `1' during VCC POR or Hard Reset, the LPC interface will decode LPC or FWH memory cycles (depending on the FWHSEL option). When the MEMEN strap option is deasserted `0' during VCC POR or Hard Reset, the LPC interface will not decode FWH or LPC memory cycles. The affects of the MEMEN strap option can be overridden by the MEMEN bit in the FWH ID Select register (see section CR54). 8.4.1.2 FWHSEL The FWHSEL strap option selects whether LPC memory or FWH cycles are decoded for the X-Bus interface, assuming the MEMEN option is asserted. Rev. 0.5 (03-24-05) Page 40 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet NOTE: If the MEMEN option is not asserted (MEMEN='0') the FWHSEL bit is a don't care and has no effect on the LPC interface. When MEMEN = `1' and the FWHSEL strap option is asserted `1' during VCC POR or Hard Reset, the LPC interface will decode FWH cycles for the X-Bus interface. When the MEMEN='1' and the FWHSEL strap option is deasserted `0' during VCC POR or Hard Reset, the LPC interface will decode LPC memory cycles for the X-Bus interface. The affects of the FWHSEL strap option can be overridden by the FWHSEL bit in the FWH ID Select register. The affects of FWHSEL can also be qualified by the IDSELEN and ID SELECT bits in the FWH ID Select register (see section CR54). 8.4.2 FWH and LPC Memory Addressing FWH cycles and LPC memory cycles received on the LPC Bus in the following system memory ranges are forwarded to the X-Bus Interface, if enabled. (see Table 8.5 - FWH Strapping Options) 000E0000h to 000FFFFFh - 128KB Legacy BIOS FF000000h to FFFFFFFFh - 16MB FWH Address Range NOTE: ICH2 only forwards memory reads/writes to the FWH that are in address ranges 000E0000h to 000FFFFFh and FF000000h to FFFFFFFFh. If the FWH or LPC memory address is from 000E0000h to 000FFFFFh, address bits 0 - 19 are forwarded to XA0 - XA19 and nXCS0 is enabled. XA20 is driven to `1' to alias the 128KB legacy system BIOS from the top of 1MB to the top of 4GB system memory. NOTE: At boot-up, all FWH memory cycles will be forwarded to the memory device on chip select 0 (nXCS0 is default) if the MEMEN and FWHSEL strapping options are configured to implement FWH memory transactions. If the FWH or LPC memory address is from FF000000h to FFFFFFFFh, address bits 0 - 20 are forwarded to XA0 - XA20 and nXCS0 is enabled. The Flash device is aligned with the top 2 MB (FFE00000h - FFFFFFFFh) of the 4 GB system memory space. NOTE: The full 16MB address space is mapped to the 2MB X-Bus interface, causing aliasing to FWH memory ranges below FFE00000h. Since no address verification is performed on address bit 21-23, the following 2MB address ranges are aliased or mapped to the X-Bus interface: FFC00000h - FFDFFFFFh, FFA00000h - FFBFFFFFh, FF800000h - FF9FFFFFh, FF600000h - FF7FFFFFh, FF400000h - FF5FFFFFh, FF200000h - FF3FFFFFh, and FF000000h - FF1FFFFFh. 8.4.3 FWH Cycle Types The cycle types supported by the FWH are: FWH Memory Read: 1 byte. FWH Memory Write: 1 byte. SMSC SIO10N268 Page 41 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet 8.4.4 8.4.4.1 Field Definitions START This one clock field indicates the start of a cycle. It is valid on the last clock that FRAME# is sampled low. The two start fields that are used for the cycle are shown in the table below. If the start field that is sampled is not one of these values, then the cycle attempted is not a FWH Memory cycle. It may be a valid memory cycle that the FWH may wish to decode, i.e., it may be of the LPC memory cycle variety. LAD[3:0] 1101 1110 INDICATION FWH Memory Read FWH Memory Write 8.4.4.2 IDSEL This one clock field is used to indicate which FWH component is being selected. The four bits transmitted over LAD[3:0] during this clock are compared with values strapped onto pins on the FWH component. If there is a match, the FWH component will continue to decode the cycle to determine which bytes are requested on a read or which bytes to update on a write. If there isn't a match, the FWH component may discard the rest of the cycle and go into a standby power state. 8.4.4.3 MSIZE This one clock field indicates the size of the transfer. This field is fixed to `0000b', other encodings are reserved for future use. A value of `0000b' corresponds to a single byte transfer. 8.4.4.4 MADDR This is a 7-clock field that gives a 28-bit memory address. This allows for up to 256MB per memory device, for a total of a 4GB addressable space. The address is transferred with the most significant nibble first. 8.4.4.5 SYNC The SYNC protocol is the same as described in the LPC specification. 8.4.4.6 TAR The TAR field is the same as described in the LPC specification. 8.4.4.7 Data The Data field is the same as described in the LPC specification. Data is transferred with the low nibble first. Rev. 0.5 (03-24-05) Page 42 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet 8.4.5 Protocol The FWH Memory cycles use a sequence of events that begin with a START field (FRAME# active) with appropriate LAD[3:0] combination, and end with the data transfer. The sections below describe the cycles in detail. 8.4.5.1 Preamble The FWH Memory transaction begins with the host driving FRAME# low. The 10-clock preamble is then initiated on the LAD[3:0] signals with a START field driven on LAD[3:0] while FRAME# is low. Following the START field is the IDSEL field. The next seven clocks are the 28-bit address from where to begin reading in the selected device. Next, the MSIZE field of 0 indicates 1 byte being transferred in the current transaction. CLK FRAME# AD[3:0] Start IDSEL MADDR - 28 Bit Address 7 Clocks Figure 8.1 - FWH Memory Cycle Preamble NOTE: Following the preamble, the host drives a TAR field on a read cycle, or drives the low nibble of data on a write cycle. See the following sections for more details. MSIZE 8.4.6 8.4.6.1 Read Cycle Single Byte To indicate that a single byte transfer cycle is being performed, the master asserts an MSIZE value of 0. For read cycles, after the preamble, the host drives a TAR field to give ownership of the bus to the FWH. After the second clock of the TAR phase, the target device assumes the bus and begins driving SYNC values. When it is ready, it drives the low nibble, then the high nibble of data, followed by a TAR to give control back to the host. CLK FRAME# AD[3:0] Preamble 10 Clocks Figure 8.2 - Single Byte Read Figure 8.2 shows a device that requires 3 SYNC clocks to access data. Since the access time can begin once the address phase has been completed, the two clocks of the TAR phase can be considered as part of the access time of the part. For example, a device with a 120ns access time could assert `0101b' for TAR SYNC DL DH TAR SMSC SIO10N268 Page 43 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet clocks 1 and 2 of the SYNC phase and `0000b' for the last clock of the SYNC phase. This would be equivalent to 5 clocks worth of access time if the device started that access at the conclusion of the MADDR phase. Once SYNC is achieved, the device returns the data in two clocks and gives ownership of the bus back to the host with a TAR phase. 8.4.7 8.4.7.1 Write Cycles Single Byte All devices that support FWH Memory Write cycles must support single byte writes. FWH Memory Write cycles use the same preamble as FWH Memory read cycles. To indicate that a single byte transfer cycle is being performed, the master asserts an MSIZE value of 0. After the address and size has been transferred, the 2-clock data phase begins. Following the data phase, bus ownership is transferred to the FWH component with a TAR cycle. Following the TAR phase, the device must assert a SYNC value of `0000b' (ready) or `1010b' (error) indicating the data has been received. Bus ownership is then given back to the master with another TAR phase. FWH Memory Writes only allow one clock for the SYNC phase. The TAR+SYNC+TAR phases at the end of FWH memory write cycles must be exactly 5 clocks. CLK FRAME# AD[3:0] Preamble 10 Clocks Figure 8.3 - Single Byte Write DL DH TAR SYNC TAR 8.4.8 Error Reporting There is no error reporting over the FWH interface for FWH Memory cycles. If an error occurs, such as an address out of range or an unsupported memory size, the cycle will continue from the host unabated. This is because these errors are the result of illegal programming, and there is no efficient error reporting method that can be done to counter the programming error. Therefore, the FWH component must not report the error conditions over the FWH interface. It must only report wait states and the `ready' condition. It may choose to log the error internally to be debugged, but it must not signal an error through the FWH interface itself. 8.4.9 8.4.9.1 FWH Cycle Examples EXAMPLE 1: FWH 1-Byte Read DRIVEN BY Host Host Host CLOCKS 1 1 1 LAD[3:0] 1101 xxxx xxxx COMMENT LAD[3:0]=1101 (FWH Memory Read) LAD[3:0]=selected FWH component Most significant nibble FIELD START IDSEL MADDR Rev. 0.5 (03-24-05) Page 44 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet FIELD MADDR MADDR MADDR MADDR MADDR MADDR MSIZE TAR TAR SYNC SYNC SYNC Data Data TAR TAR DRIVEN BY Host Host Host Host Host Host Host Host Special Peripheral Peripheral Peripheral Peripheral Peripheral Peripheral Special CLOCKS 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 LAD[3:0] xxxx xxxx xxxx xxxx xxxx xxxx 0000 1111 1111 0101 0101 0000 xxxx xxxx 1111 1111 COMMENT . . . . . Least significant nibble Number of bytes= 1 Host drives LAD[3:0] high Not driven Sync=0101 (Sync not achieved yet) Sync=0101 (Sync not achieved yet) Sync=0000 (Sync achieved with no error) Least significant nibble of byte Most significant nibble of byte Peripheral drives LAD[3:0] high Not driven 8.4.9.2 EXAMPLE 2: FWH 1-Byte Write DRIVEN BY Host Host Host Host Host Host Host Host Host Host Host Host Host Special Peripheral Peripheral Special CLOCKS 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 LAD[3:0] 1110 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 xxxx xxxx 1111 1111 0000 1111 1111 COMMENT LAD[3:0]=1110 (FWH Memory Write) LAD[3:0]=selected FWH component Most significant nibble . . . . . Least significant nibble Number of bytes= 1 Least significant nibble of byte Most significant nibble of byte Host drives LAD[3:0] high Not driven Sync=0000 (Sync achieved, no errors) Peripheral drives LAD[3:0] high Not driven FIELD START IDSEL MADDR MADDR MADDR MADDR MADDR MADDR MADDR MSIZE Data Data TAR TAR SYNC TAR TAR 8.5 NOTE: X-Bus Interface (LPC Mode Only) The X-Bus interface is only accessible in LPC Mode. The X-Bus interface is designed to support memory and I/O devices with 21 address pins (XA0-XA20), an 8-bit data bus (XD0 - XD7), and Read and Write signals. This interface offers one chip select to access memory devices (nXCS0) and two chip selects to access I/O devices (nXCS1 and nXCS2). Note that nXCS2 is muxed on the GP22 pin (GP22/IRMODE/IRRX3/nXCS2) NOTE: It also provides a read strobe (nXRD) and a write strobe (nXWR). These pins default to their inactive state (i.e., inactive state=high) on VCC POR and are tristate when VCC=0V and VTR 3.3V. (These pins must be pulled up to VCC through an external resistor.) Page 45 Rev. 0.5 (03-24-05) SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet I/O devices located on the X-Bus interface may be accessed by I/O transactions on the LPC interface. Memory or Flash devices located on the X-Bus interface may be accessed by LPC Memory or Firmware Hub (FWH) cycles via the LPC interface. See sections 8.3.4.3 Memory Read and Write Cycles on page 37 and 8.4 FWH Interface (LPC Mode Only) on page 40 for decoding FWH cycles. NOTE: Chip Select nXCS[0] can be disabled from going active for a memory access by settting the corresponding enable bit to `0', which is located in the X-Bus Chip Select 0 Register. Chip Selects nXCS1and nXCS2 can be disabled from going active for an I/O access by setting the corresponding disable bit to `1', which is located in the associated Base I/O Address x - Low Byte register. These bits allow each chip select to be individually enabled or disabled for either memory or I/O transactions. 8.5.1 I/O Cycles The X-bus interface allows the SIO10N268 - LPC MODE to interface to as many as 2 external components that have an 8 bit data bus. Devices located on nXCS1 and nXCS2 are accessable by LPC I/O transactions. These devices may have their Base I/O Addresses located on 2, 4, or 16 byte boundaries depending on the X-Bus mode of operation. (See section 10.5 Logical Device Base I/O Address and Range on page 215 for valid Base I/O Addresses for the X-Bus interface.) The SIO10N268 - LPC MODE performs 16-bit address qualification on the X-Bus base I/O addresses. That is, the upper 4-bits, bits[15:12], must be `0'. The X-Bus interface offers three different modes of operation for I/O devices on both I/O chip selects (nXCS1 and nXCS2). In Mode 1, a 10-bit compare is performed on address bits[11:2] and address bits[1:0] are forwarded to XA1 and XA0 respectively. In Mode 2, an 8-bit compare is performed on address bits[11:4] and address bits[3:0] are forwarded to XA3 to XA0 respectively. In Mode 3, a 10-bit address compare is performed on address bits[11:3] and bits[1] and if address is valid and bit[0]=0 then address bit[2] is forwarded to XA2 . The chip select outputs are generated by logic that compares the LPC I/O address bits with the X-bus base I/O address configuration registers. The mode of operation determines the number of valid address pins that the X-bus interface provides, as well as the number of bits in the base I/O addresses. The mode is chosen via bits[1:0] of the X-Bus I/O Select Configuration Register located at CR52. The options for X-bus modes are as follows: Mode 1: The X-bus base I/O address configuration registers contain address bits A11 through A8 and A7 through A2, respectively. A1 and A0 pass directly through to XA1 and XA0, respectively. The chip selects only become active (low) for the LPC bus cycle in which the address match occurs. Mode 2: The X-bus base I/O address configuration registers contain address bits A11 through A8 and A7 through A4, respectively. A3, A2, A1 and A0 pass directly through to XA3, XA2, XA1 and XA0, respectively. The chip selects only become active (low) for the LPC bus cycle in which the address match occurs. Mode 3: The X-bus base I/O address configuration registers contain address bits A11 through A8, A7 though A3, and A1. A2 passes directly through to XA2. A2 is used to select between the registers at base address offset 0 and offset of 4. This mode allows communication with up to three register pairs at a programmable base address and fixed offset of +4, for example (60,64), (62,66), (68,6C). The chip selects only become active (low) for the LPC bus cycle in which the address match occurs. A0 (address bit 0 from LPC bus) must be `0' since registers may only be accessed on even-byte boundaries. That is, only even addresses are valid since the part checks that bit A0 is 0. Each X-bus chip select base address register has an associated "write protect" bit that can only be set once, and is reset by VCC POR and PCI Reset (i.e., Hard Reset). When this bit is set, it prevents the base address configuration registers (high byte and low byte) for each chip select from being written. This security feature ensures that the base address and disable bit for each chip select can only be set by BIOS and cannot be corrupted by any virus software. This bit is part of the X-bus Low Address Byte Configuration register. Rev. 0.5 (03-24-05) Page 46 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet Each X-bus chip select has an associated disable bit. This bit allows each chip select to be individually enabled or disabled. This bit is part of the X-bus Low Address Byte Configuration register. Setting the disable bit prevents the associated chip select from going active, and prevents the X-bus read and write strobes from going active. In addition, when the disable bit is set, the mode dependent address pins (XA0, XA1, XA2, XA3) will not toggle (they will stay in their previous state). The disable bits default to disabled following a VCC POR and Hard Reset. Once enabled, following a VCC POR, the chip selects are held inactive until a valid LPC I/O cycle results in an address match with the base address register. The read and write strobes have address setup and hold times, and pulse widths, that are compatible with X-Bus timing of the Intel PIIX4. The strobes will only become active during an LPC cycle in which the LPC address matches the corresponding X-bus address. 8.5.1.1 Conceptual Diagrams of X-Bus I/O interface The following diagrams are a conceptual diagrams to illustrate the activation of the X-Bus I/O chip selects. It is not intended to indicate the actual implementation. The following figure shows the X-Bus Interface in mode 1. LPC Address 12 8 LPC Data LPC R/W Command I/O ReadnXRD Active I/O WritenXWR Active 8-bit Data Bus X-Bus CS1 Base Address Configuration Register Disable X-Bus CS2 Base Address Configuration Register Disable 10-bit Address Comparator (Bits[15:12]=0) nXCS1 10-bit Address Comparator (Bits[15:12]=0) a Alternate Function Mux nXCS2 Alternate Pin Functions (GP22/IRMODE/IRRX3) XA0 XA1 a - Alternate Function Select bits SMSC SIO10N268 Page 47 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet Figure 8.4 - X-Bus Interface, Mode 1 The following figure shows the X-bus interface in mode 2. LPC Address 12 8 LPC Data LPC R/W Command I/O ReadnXRD Active I/O WritenXWR Active 8-bit Data Bus X-Bus CS1 Base Address Configuration Register Disable X-Bus CS2 Base Address Configuration Register Disable 8-bit Address Comparator (Bits[15:12]=0) nXCS1 8-bit Address Comparator (Bits[15:12]=0) a Alternate Function Mux nXCS2 Alternate Pin Functions (GP22/IRMODE/IRRX3) XA0 XA1 XA2 XA3 a - Alternate Function Select bits Figure 8.5 - X-Bus Interface, Mode 2 Rev. 0.5 (03-24-05) Page 48 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet The following figure shows the X-bus interface in mode 3. LPC Address 12 8 LPC Data LPC R/W Command I/O ReadnXRD Active I/O WritenXWR Active 8-bit Data Bus X-Bus CS1 Base Address Configuration Register Disable X-Bus CS2 Base Address Configuration Register Disable 10-bit Address Comparator (Bits[15:12]=0 & Bit[0]=0) nXCS1 10-bit Address Comparator (Bits[15:12]=0 & Bit[0]=0) a Alternate Function Mux nXCS2 Alternate Pin Functions (GP22/IRMODE/IRRX3) XA2 a - Alternate Function Select bits Figure 8.6 - X-Bus Interface, Mode 3 8.5.2 Memory Cycles All Firmware Hub and LPC memory cycles that have been accepted and decoded by the LPC interface are forwarded to the X-Bus interface and are enabled on nXCS0. See section 8.4.2 FWH and LPC Memory Addressing for a description of the memory cycles forwarded to the X-Bus interface. This interface is capable of accessing up to 2MB (16Mbit) of external flash memory in 8-bit words only. The X-Bus Chip Select 0 Register at offset CR53 is used to configure access for memory cycles to the XBus interface. On a VCC POR and Hard Reset this chip select defaults to be enabled. Chip select 0 (nXCS0) may be disabled by setting bit[7] of the X-Bus Chip Select 0 Register to `0'. SMSC SIO10N268 Page 49 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet The X-Bus supports flash speed selection by offering a programmable read/write pulse width (see section 12.4.3 X-Bus Memory Cycle Timing on page 230. The read/write pulse width is determined by the Pulse Width Selection bits located in X-Bus Chip Select 0 Register at offset CR53. These bits allow the read/write strobe to be held active for a minimum of 60, 90, 120, or 150 nsec. The X-Bus Chips Select 0 Register offers a write protect bit. This bit affords the BIOS the ability to program CR53 for a particular configuration, which cannot be altered until a VCC POR or Hard Reset. NOTE: To tristate the X-Bus for production line Flash update put the device in XNOR chain test mode. 8.6 ISA Interface (ISA Mode Only) ISA Mode is enabled by pulling pin 54 (LPC_ISA) directly to VCC - a pull-up resistor should not be used. The ISA interface is a standard AT (Advanced Technology) interface, that is compatible with the ISA (Industry Standard Architecture) as documented by IEEE (IEEE P996 compatible). This interface supports I/O and DMA transactions as defined by this defacto standard. In addition this interface has been modified to have the option of supporting ISA devices that do not have an AEN output signal (Devices like the Intel 440MX chipset). The following sections define the signals on the ISA interface and the modifications made to support special chipsets like the 440MX. NOTE: For ISA timing see section 12.5 Host Timing (ISA Mode Only) on page 232. Table 8.6 - Description of ISA Signals NAME System Data Bus 0-7 SYMBOL SD0-SD7 DESCRIPTION The system data bus connection used by the host microprocessor to transmit data to and from the chip. These pins are in a high-impedance state when not in the output mode. This active low signal is issued by the host microprocessor to indicate an I/O read operation. This active low signal is issued by the host microprocessor to indicate an I/O write operation. Active high Address Enable indicates DMA operations on the host data bus. Used internally to qualify appropriate address decodes. (See section 8.6.1 AEN signal following table.) These host address bits determine the I/O address to be accessed during nIOR and nIOW cycles. These bits are latched internally by the leading edge of nIOR and nIOW. All internal address decodes use the full A0 to A15 address bits. These active high outputs are the DMA request for byte transfers of data between the host and the chip. These signals are cleared on the last byte of the data transfer by the nDACK signal going low (or by nIOR going low if nDACK was already low as in demand mode). These are active low inputs acknowledging the request for a DMA transfer of data between the host and the chip. These inputs enable the DMA read or write internally. This signal indicates that DMA data transfer is complete. TC is only accepted when nDACK_x is low. In AT and PS/2 model 30 modes, TC is active high and in PS/2 mode, TC is active low. Serial IRQ pin used with the PCI_CLK pin to transfer SIO10N268 interrupts to the host. I/O Read I/O Write Address Enable nIORD nIOWR AEN System Address Bus SA0-SA15 DMA Request 0, 1, 2, 3 nDMA Acknowl-edge 0, 1, 2, 3 Terminal Count DRQ_0 DRQ_1 DRQ_2 DRQ_3 nDACK_0 nDACK_1 nDACK_2 nDACK_3 TC Serial IRQ SER_IRQ Rev. 0.5 (03-24-05) Page 50 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet NAME PCI Clock SYMBOL PCI_CLK ISA Reset Drive RESET_DRV I/O Channel Ready (Note 8.7) Power Management Event System Management Event Note 8.7 IOCHRDY IO_PME# IO_SMI# DESCRIPTION 33MHz PCI clock input, used with the SIRQ and the CLKRUN# pins to serially transfer SIO10N268 interrupts to the host. Note: If serial IRQs are not supported then the PCI Clock input may be connected to the PCI clock or 14.318MHz clock source. This active high signal resets the chip and must be valid for 500ns minimum. The effect on the internal registers is described in the appropriate section. The configuration registers are not affected by this reset. This pin is pulled low to extend the read/write command. IOCHRDY can be used by the IRCC and by the Parallel Port in EPP mode. Power Mgt Event signal. Allows the SIO10N268 to request wakeup. System Mgt Interrupt signal. Allows the SIO10N268 to notify the host system that an event has occurred. An external pull-up must be provided for IOCHRDY. The SER_IRQ, PCI_CLK, IO_PME#, and IO_SMI# signals are considered part of the host interface. They are available in both LPC Mode and ISA Mode. 8.6.1 AEN signal The AEN signal is used to indicate that a DMA operation is active on the host bus. It is used to prevent I/O devices from responding to DMA transactions. Not all devices that provide an ISA interface support this feature. For example, the 440MX chipset does not supply an AEN signal, instead it drives the address bus to 0000h during a DMA I/O cycle to indicate a DMA transaction is occuring. The SIO10N268 has implemented two modes of operation that are selectable via the AEN control bit located in the Clock/AEN Control Register located at offset CR1E. This bit is implemented as shown. bit[1] AEN Control 1) 2) If the AEN Control bit is set to `0' the internal AEN signal will be asserted if the AEN pin is high OR if SA[0:15]=0000h (default). If the AEN Control bit is set to `1' the internal AEN signal will asserted only when the AEN pin is high. NOTE: System designers using the 440MX chipset should ground the AEN pin to prevent the AEN pin from floating, thereby creating false DMA cycles. The SIO10N268 only responds to I/O addresses above 100h. 8.7 Floppy Disk Controller The Floppy Disk Controller (FDC) provides the interface between a host microprocessor and the floppy disk drives. The FDC integrates the functions of the Formatter/Controller, Digital Data Separator, Write Precompensation and Data Rate Selection logic for an IBM XT/AT compatible FDC. The true CMOS 765B core guarantees 100% IBM PC XT/AT compatibility in addition to providing data overflow and underflow protection. The FDC is compatible to the 82077AA using SMSC's proprietary floppy disk controller core. The SIO10N268 supports one floppy disk drive directly through the FDC interface pins and two floppy disk drives the FDC interface on the parallel port pins. It can also be configured to support on drive on the FDC interface pins and one drive on the parallel port pins. SMSC SIO10N268 Page 51 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet 8.7.1 FDC Internal Registers The Floppy Disk Controller contains eight internal registers that facilitate the interfacing between the host microprocessor and the disk drive. Table 8.7 shows the addresses required to access these registers. Registers other than the ones shown are not supported. The rest of the description assumes that the primary addresses have been selected. Table 8.7 - Status, Data and Control Registers (Shown with base addresses of 3F0 and 370) SECONDARY R/W REGISTER ADDRESS 370 R Status Register A (SRA) 371 R Status Register B (SRB) 372 R/W Digital Output Register (DOR) 373 R/W Tape Drive Register (TDR) 374 R Main Status Register (MSR) 374 W Data Rate Select Register (DSR) 375 R/W Data (FIFO) 376 Reserved 377 R Digital Input Register (DIR) 377 W Configuration Control Register (CCR) PRIMARY ADDRESS 3F0 3F1 3F2 3F3 3F4 3F4 3F5 3F6 3F7 3F7 8.7.1.1 Status Register A (SRA) Address 3F0 READ ONLY This register is read-only and monitors the state of the internal interrupt signal and several disk interface pins in PS/2 and Model 30 modes. The SRA can be accessed at any time when in PS/2 mode. In the PC/AT mode the data bus pins D0 - D7 are held in a high impedance state for a read of address 3F0. PS/2 Mode 7 INT PENDING 0 6 nDRV2 1 5 STEP 0 4 3 2 nTRK0 HDSEL nINDEX N/A 0 N/A 1 nWP N/A 0 DIR 0 RESET COND. BIT 0 DIRECTION Active high status indicating the direction of head movement. A logic "1" indicates inward direction; a logic "0" indicates outward direction. BIT 1 nWRITE PROTECT Active low status of the WRITE PROTECT disk interface input. A logic "0" indicates that the disk is write protected. BIT 2 nINDEX Active low status of the INDEX disk interface input. Rev. 0.5 (03-24-05) Page 52 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet BIT 3 HEAD SELECT Active high status of the HDSEL disk interface input. A logic "1" selects side 1 and a logic "0" selects side 0. BIT 4 nTRACK 0 Active low status of the TRK0 disk interface input. BIT 5 STEP Active high status of the STEP output disk interface output pin. BIT 6 nDRV2 This function is not supported. This bit is always read as "1". BIT 7 INTERRUPT PENDING Active high bit indicating the state of the Floppy Disk Interrupt output. PS/2 Model 30 Mode 7 INT PENDING RESET COND. BIT 0 nDIRECTION Active low status indicating the direction of head movement. A logic "0" indicates inward direction; a logic "1" indicates outward direction. BIT 1 WRITE PROTECT Active high status of the WRITE PROTECT disk interface input. A logic "1" indicates that the disk is write protected. BIT 2 INDEX Active high status of the INDEX disk interface input. BIT 3 nHEAD SELECT Active low status of the HDSEL disk interface input. A logic "0" selects side 1 and a logic "1" selects side 0. BIT 4 TRACK 0 Active high status of the TRK0 disk interface input. 0 6 DRQ 0 5 STEP F/F 0 4 TRK0 N/A 3 2 nHDSEL INDEX 1 N/A 1 WP N/A 0 nDIR 1 SMSC SIO10N268 Page 53 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet BIT 5 STEP Active high status of the latched STEP disk interface output pin. This bit is latched with the STEP output going active, and is cleared with a read from the DIR register, or with a hardware or software reset. BIT 6 DMA REQUEST Active high status of the DMA request pending. BIT 7 INTERRUPT PENDING Active high bit indicating the state of the Floppy Disk Interrupt. 8.7.1.2 Status Register B (SRB) Address 3F1 READ ONLY This register is read-only and monitors the state of several disk interface pins in PS/2 and model 30 modes. The SRB can be accessed at any time when in PS/2 mode. In the PC/AT mode the data bus pins D0 - D7 are held in a high impedance state for a read of address 3F1. PS/2 Mode 7 1 RESET COND. 1 6 1 1 5 4 3 2 DRIVE WDATA RDATA WGATE SEL0 TOGGLE TOGGLE 0 0 0 0 1 MOT EN1 0 0 MOT EN0 0 BIT 0 MOTOR ENABLE 0 Active high status of the MTR0 disk interface output pin. This bit is low after a hardware reset and unaffected by a software reset. BIT 1 MOTOR ENABLE 1 Active high status of the MTR1 disk interface output pin. This bit is low after a hardware reset and unaffected by a software reset. BIT 2 WRITE GATE Active high status of the WGATE disk interface output. BIT 3 READ DATA TOGGLE Every inactive edge of the RDATA input causes this bit to change state. BIT 4 WRITE DATA TOGGLE Every inactive edge of the WDATA input causes this bit to change state. BIT 5 DRIVE SELECT 0 Reflects the status of the Drive Select 0 bit of the DOR (address 3F2 bit 0). This bit is cleared after a hardware reset and it is unaffected by a software reset. Rev. 0.5 (03-24-05) Page 54 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet BIT 6 RESERVED Always read as a logic "1". BIT 7 RESERVED Always read as a logic "1". PS/2 Model 30 Mode 7 nDRV2 RESET COND. N/A 6 nDS1 1 5 nDS0 1 4 WDATA F/F 0 3 RDATA F/F 0 2 WGATE F/F 0 1 nDS3 1 0 nDS2 1 BIT 0 nDRIVE SELECT 2 The DS2 disk interface is not supported. BIT 1 nDRIVE SELECT 3 The DS3 disk interface is not supported. BIT 2 WRITE GATE Active high status of the latched WGATE output signal. This bit is latched by the active going edge of WGATE and is cleared by the read of the DIR register. BIT 3 READ DATA Active high status of the latched RDATA output signal. This bit is latched by the inactive going edge of RDATA and is cleared by the read of the DIR register. BIT 4 WRITE DATA Active high status of the latched WDATA output signal. This bit is latched by the inactive going edge of WDATA and is cleared by the read of the DIR register. This bit is not gated with WGATE. BIT 5 nDRIVE SELECT 0 Active low status of the DS0 disk interface output. BIT 6 nDRIVE SELECT 1 Active low status of the DS1 disk interface output. BIT 7 nDRV2 Active low status of the DRV2 disk interface input. Note: This function is not supported. SMSC SIO10N268 Page 55 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet 8.7.1.3 Digital Output Register (DOR) Address 3F2 READ/WRITE The DOR controls the drive select and motor enables of the disk interface outputs. It also contains the enable for the DMA logic and a software reset bit. The contents of the DOR are unaffected by a software reset. The DOR can be written to at any time. 7 MOT EN3 0 6 MOT EN2 0 5 MOT EN1 0 4 MOT EN0 0 3 DMAEN 0 2 1 0 nRESE DRIVE DRIVE T SEL1 SEL0 0 0 0 RESET COND. BIT 0 and 1 DRIVE SELECT These two bits are binary encoded for the drive selects, thereby allowing only one drive to be selected at one time. BIT 2 nRESET A logic "0" written to this bit resets the Floppy disk controller. This reset will remain active until a logic "1" is written to this bit. This software reset does not affect the DSR and CCR registers, nor does it affect the other bits of the DOR register. The minimum reset duration required is 100ns, therefore toggling this bit by consecutive writes to this register is a valid method of issuing a software reset. BIT 3 DMAEN PC/AT and Model 30 Mode: Writing this bit to logic "1" will enable the DMA and interrupt functions. This bit being a logic "0" will disable the DMA and interrupt functions. This bit is a logic "0" after a reset and in these modes. PS/2 Mode: In this mode the DMA and interrupt functions are always enabled. During a reset, this bit will be cleared to a logic "0". BIT 4 MOTOR ENABLE 0 This bit controls the MTR0 disk interface output. A logic "1" in this bit will cause the output pin to go active. BIT 5 MOTOR ENABLE 1 This bit controls the MTR1 disk interface output. A logic "1" in this bit will cause the output pin to go active. BIT 6 MOTOR ENABLE 2 The MTR2 disk interface output is not supported. BIT 7 MOTOR ENABLE 3 The MTR3 disk interface output is not supported. DRIVE 0 1 DOR VALUE 1CH 2DH Rev. 0.5 (03-24-05) Page 56 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet Table 8.8 - Internal 2 Drive Decode (Normal) DIGITAL OUTPUT REGISTER Bit 5 X 1 0 Bit 4 1 X 0 Bit1 0 0 X Bit 0 0 1 X DRIVE SELECT OUTPUTS (ACTIVE LOW) nDS1 1 0 1 nDS0 0 1 1 MOTOR ON OUTPUTS (ACTIVE LOW) nMTR1 nMTR0 nBIT 5 nBIT 4 nBIT 5 nBIT 4 nBIT 5 nBIT 4 Table 8.9 - Internal 2 Drive Decode (Drives 0 and 1 Swapped) DIGITAL OUTPUT REGISTER Bit 5 X 1 0 Bit 4 1 X 0 Bit1 0 0 X Bit 0 0 1 X DRIVE SELECT OUTPUTS (ACTIVE LOW) nDS1 0 1 1 nDS0 1 0 1 MOTOR ON OUTPUTS (ACTIVE LOW) nMTR1 nMTR0 nBIT 4 nBIT 5 nBIT 4 nBIT 5 nBIT 4 nBIT 5 8.7.1.4 Tape Drive Register (TDR) Address 3F3 READ/WRITE The Tape Drive Register (TDR) is included for 82077 software compatibility and allows the user to assign tape support to a particular drive during initialization. Any future references to that drive automatically invokes tape support. The TDR Tape Select bits TDR.[1:0] determine the tape drive number. Table 8.10 illustrates the Tape Select Bit encoding. Note that drive 0 is the boot device and cannot be assigned tape support. The remaining Tape Drive Register bits TDR.[7:2] are tristated when read. The TDR is unaffected by a software reset. Table 8.10 - Tape Select Bits TAPE SEL1 (TDR.1) 0 0 1 1 TAPE SEL0 (TDR.0) 0 1 0 1 DRIVE SELECTED None 1 2 3 Note 8.8 The SIO10N268 supports one floppy drive directly on the FDC interface pins and two floppy drives on the Parallel Port. Normal Floppy Mode Normal mode. Register 3F3 contains only bits 0 and 1. When this register is read, bits 2 - 7 are `0'. DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 tape sel1 DB0 tape sel0 REG 3F3 SMSC SIO10N268 Page 57 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet Enhanced Floppy Mode 2 (OS2) Register 3F3 for Enhanced Floppy Mode 2 operation. DB7 DB6 REG 3F3 Reserved Reserved DB5 DB4 Drive Type ID DB3 DB2 Floppy Boot Drive DB1 tape sel1 DB0 tape sel0 Table 8.11 - Drive Type ID DIGITAL OUTPUT REGISTER Bit 1 Bit 0 0 0 0 1 1 0 1 1 Note 8.9 CR06-Bx = Configuration Register 06, Bit x. REGISTER 3F3 - DRIVE TYPE ID Bit 5 Bit 4 CR06 - B1 CR06 - B0 CR06 - B3 CR06 - B2 CR06 - B5 CR06 - B4 CR06 - B7 CR06 - B6 8.7.1.5 Data Rate Select Register (DSR) Address 3F4 WRITE ONLY This register is write only. It is used to program the data rate, amount of write precompensation, power down status, and software reset. The data rate is programmed using the Configuration Control Register (CCR) not the DSR, for PC/AT and PS/2 Model 30 applications. Other applications can set the data rate in the DSR. The data rate of the floppy controller is the most recent write of either the DSR or CCR. The DSR is unaffected by a software reset. A hardware reset will set the DSR to 02H, which corresponds to the default precompensation setting and 250 Kbps. 7 6 S/W POWER RESET DOWN 0 0 5 0 0 4 PRECOMP2 0 3 PRECOMP1 0 2 1 0 PREDRATE DRATE COMP0 SEL1 SEL0 0 1 0 RESET COND. BIT 0 and 1 DATA RATE SELECT These bits control the data rate of the floppy controller. See Table 8.13 for the settings corresponding to the individual data rates. The data rate select bits are unaffected by a software reset, and are set to 250 Kbps after a hardware reset. BIT 2 through 4 PRECOMPENSATION SELECT These three bits select the value of write precompensation that will be applied to the WDATA output signal. Table 8.12 shows the precompensation values for the combination of these bits settings. Track 0 is the default starting track number to start precompensation. This starting track number can be changed by the configure command. BIT 5 UNDEFINED Should be written as a logic "0". Rev. 0.5 (03-24-05) Page 58 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet BIT 6 LOW POWER A logic "1" written to this bit will put the floppy controller into manual low power mode. The floppy controller clock and data separator circuits will be turned off. The controller will come out of manual low power mode after a software reset or access to the Data Register or Main Status Register. BIT 7 SOFTWARE RESET This active high bit has the same function as the DOR RESET (DOR bit 2) except that this bit is self clearing. NOTE: The DSR is Shadowed in the Floppy Data Rate Select Shadow Register, located in the Configuration section (CR14). Table 8.12 - Precompensation Delays PRECOMP 432 111 001 010 011 100 101 110 000 PRECOMPENSATION DELAY (nsec) <2Mbps 2Mbps 0.00 0 41.67 20.8 83.34 41.7 125.00 62.5 166.67 83.3 208.33 104.2 250.00 125 Default Default Default: See Table 8.15 Table 8.13 - Data Rates DRIVE RATE DRT1 0 0 0 0 0 0 0 0 1 1 1 1 DRT0 0 0 0 0 1 1 1 1 0 0 0 0 DATA RATE SEL1 1 0 0 1 1 0 0 1 1 0 0 1 SEL0 1 0 1 0 1 0 1 0 1 0 1 0 DATA RATE MFM 1Meg 500 300 250 1Meg 500 500 250 1Meg 500 2Meg 250 FM --250 150 125 --250 250 125 --250 --125 DENSEL 1 1 0 0 1 1 0 0 1 1 0 0 DRATE(1) 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Drive Rate Table (Recommended) 00 = 360K, 1.2M, 720K, 1.44M and 2.88M Vertical Format 01 = 3-Mode Drive 10 = 2 Meg Tape SMSC SIO10N268 Page 59 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet Note 8.10 The DRATE and DENSEL values are mapped onto the DRVDEN pins. Table 8.14 - DRVDEN Mapping0 DT1 0 DT0 0 DRVDEN1 (1) DRATE0 DRVDEN0 (1) DENSEL DRIVE TYPE 4/2/1 MB 3.5" 2/1 MB 5.25" FDDS 2/1.6/1 MB 3.5" (3-MODE) PS/2 1 0 1 0 1 1 DRATE0 DRATE0 DRATE1 DRATE1 nDENSEL DRATE0 Table 8.15 - Default Precompensation Delays DATA RATE 2 Mbps 1 Mbps 500 Kbps 300 Kbps 250 Kbps PRECOMPENSATION DELAYS 20.8 ns 41.67 ns 125 ns 125 ns 125 ns 8.7.1.6 Main Status Register (MSR) Address 3F4 READ ONLY The Main Status Register is a read-only register and indicates the status of the disk controller. The Main Status Register can be read at any time. The MSR indicates when the disk controller is ready to receive data via the Data Register. It should be read before each byte transferring to or from the data register except in DMA mode. No delay is required when reading the MSR after a data transfer. 7 RQM 6 DIO 5 NON DMA 4 CMD BUSY 3 2 1 DRV1 BUSY 0 DRV0 BUSY Reserved Reserved BIT 0 1 DRV x BUSY These bits are set to 1s when a drive is in the seek portion of a command, including implied and overlapped seeks and recalibrates. BIT 4 COMMAND BUSY This bit is set to a 1 when a command is in progress. This bit will go active after the command byte has been accepted and goes inactive at the end of the results phase. If there is no result phase (Seek, Recalibrate commands), this bit is returned to a 0 after the last command byte. BIT 5 NON-DMA Reserved, read `0'. This part does not support non-DMA mode. BIT 6 DIO Rev. 0.5 (03-24-05) Page 60 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet Indicates the direction of a data transfer once a RQM is set. A 1 indicates a read and a 0 indicates a write is required. BIT 7 RQM Indicates that the host can transfer data if set to a 1. No access is permitted if set to a 0. 8.7.1.7 Data Register (FIFO) Address 3F5 READ/WRITE All command parameter information, disk data and result status are transferred between the host processor and the floppy disk controller through the Data Register. Data transfers are governed by the RQM and DIO bits in the Main Status Register. The Data Register defaults to FIFO disabled mode after any form of reset. This maintains PC/AT hardware compatibility. The default values can be changed through the Configure command (enable full FIFO operation with threshold control). The advantage of the FIFO is that it allows the system a larger DMA latency without causing a disk error. Table 8.16 gives several examples of the delays with a FIFO. The data is based upon the following formula: Threshold # x 1 x 8 - 1.5 s = DELAY DATA RATE At the start of a command, the FIFO action is always disabled and command parameters are sent based upon the RQM and DIO bit settings. As the command execution phase is entered, the FIFO is cleared of any data to ensure that invalid data is not transferred. An overrun or underrun will terminate the current command and the transfer of data. Disk writes will complete the current sector by generating a 00 pattern and valid CRC. Reads require the host to remove the remaining data so that the result phase may be entered. Table 8.16 - FIFO Service Delay FIFO THRESHOLD EXAMPLES 1 byte 2 bytes 8 bytes 15 bytes FIFO THRESHOLD EXAMPLES 1 byte 2 bytes 8 bytes 15 bytes FIFO THRESHOLD EXAMPLES 1 byte 2 bytes 8 bytes 15 bytes MAXIMUM DELAY TO SERVICING AT 2 Mbps DATA RATE 1 x 4 s - 1.5 s = 2.5 s 2 x 4 s - 1.5 s = 6.5 s 8 x 4 s - 1.5 s = 30.5 s 15 x 4 s - 1.5 s = 58.5 s MAXIMUM DELAY TO SERVICING AT 1 Mbps DATA RATE 1 x 8 s - 1.5 s = 6.5 s 2 x 8 s - 1.5 s = 14.5 s 8 x 8 s - 1.5 s = 62.5 s 15 x 8 s - 1.5 s = 118.5 s MAXIMUM DELAY TO SERVICING AT 500 Kbps DATA RATE 1 x 16 s - 1.5 s = 14.5 s 2 x 16 s - 1.5 s = 30.5 s 8 x 16 s - 1.5 s = 126.5 s 15 x 16 s - 1.5 s = 238.5 s SMSC SIO10N268 Page 61 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet 8.7.1.8 Digital Input Register (DIR) Address 3F7 READ ONLY This register is read-only in all modes. PC-AT Mode 7 DSK CHG N/A 6 0 N/A 5 0 N/A 4 0 N/A 3 0 N/A 2 0 N/A 1 0 N/A 0 0 N/A RESET COND. BIT 0 - 6 UNDEFINED The data bus outputs D0 - 6 are read as `0'. BIT 7 DSKCHG This bit monitors the pin of the same name and reflects the opposite value seen on the disk cable or the value programmed in the Force FDD Status Change Register (CR17). see the Configuration section for register description. PS/2 Mode 7 DSK CHG N/A 6 1 N/A 5 1 N/A 4 1 N/A 3 1 N/A 2 1 0 DRATE DRATE nHIGH SEL1 SEL0 nDENS N/A N/A 1 RESET COND. BIT 0 nHIGH DENS This bit is low whenever the 500 Kbps or 1 Mbps data rates are selected, and high when 250 Kbps and 300 Kbps are selected. BITS 1 - 2 DATA RATE SELECT These bits control the data rate of the floppy controller. See Table 8.13 for the settings corresponding to the individual data rates. The data rate select bits are unaffected by a software reset, and are set to 250 Kbps after a hardware reset. BITS 3 - 6 UNDEFINED Always read as a logic "1" Rev. 0.5 (03-24-05) Page 62 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet BIT 7 DSKCHG This bit monitors the pin of the same name and reflects the opposite value seen on the disk cable or the value programmed in the Force Disk Change Register (CR17). See the Configuration section for register description. Model 30 Mode 7 DSK CHG N/A 6 0 0 5 0 0 4 0 0 3 2 1 0 DMAEN NOPREC DRATE DRATE SEL1 SEL0 0 0 1 0 RESET COND. BITS 0 - 1 DATA RATE SELECT These bits control the data rate of the floppy controller. See Table 8.13 for the settings corresponding to the individual data rates. The data rate select bits are unaffected by a software reset, and are set to 250 Kbps after a hardware reset. BIT 2 NOPREC This bit reflects the value of NOPREC bit set in the CCR register. BIT 3 DMAEN This bit reflects the value of DMAEN bit set in the DOR register bit 3. BITS 4 - 6 UNDEFINED Always read as a logic "0" BIT 7 DSKCHG This bit monitors the pin of the same name and reflects the opposite value seen on the disk cable or the value programmed in the Force Disk Change Register (CR17). See the Configuration section for register description. 8.7.1.9 Configuration Control Register (CCR) Address 3F7 WRITE ONLY PC/AT and PS/2 Modes 7 0 RESET COND. N/A 6 0 N/A 5 0 N/A 4 0 N/A 3 0 N/A 2 0 N/A 1 0 DRATE DRATE SEL1 SEL0 1 0 BIT 0 and 1 DATA RATE SELECT 0 and 1 These bits determine the data rate of the floppy controller. See Table 8.13 for the appropriate values. SMSC SIO10N268 Page 63 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet BIT 2 - 7 RESERVED Should be set to a logical "0". PS/2 Model 30 Mode 7 0 RESET COND. N/A 6 0 N/A 5 0 N/A 4 0 N/A 3 0 N/A 2 1 0 NOPREC DRATE DRATE SEL1 SEL0 N/A 1 0 BIT 0 and 1 DATA RATE SELECT 0 and 1 These bits determine the data rate of the floppy controller. See Table 8.13 for the appropriate values. BIT 2 NO PRECOMPENSATION This bit can be set by software, but it has no functionality. It can be read by bit 2 of the DSR when in Model 30 register mode. Unaffected by software reset. BIT 3 - 7 RESERVED Should be set to a logical "0" Table 8.14 shows the state of the DENSEL pin. The DENSEL pin is set high after a hardware reset and is unaffected by the DOR and the DSR resets. 8.7.2 Status Register Encoding During the Result Phase of certain commands, the Data Register contains data bytes that give the status of the command just executed. Table 8.17 - Status Register 0 BIT NO. 7,6 SYMBOL IC NAME DESCRIPTION Interrupt Code 00 - Normal termination of command. The specified command was properly executed and completed without error. 01 - Abnormal termination of command. Command execution was started, but was not successfully completed. 10 - Invalid command. The requested command could not be executed. 11 - Abnormal termination caused by Polling. Seek End The FDC completed a Seek, Relative Seek or Recalibrate command (used during a Sense Interrupt Command). Equipment The TRK0 pin failed to become a "1" after: Check 1. 255 step pulses in the Recalibrate command. 2. The Relative Seek command caused the FDC to step outward beyond Track 0. Unused. This bit is always "0". Page 64 SMSC SIO10N268 5 SE 4 EC 3 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet BIT NO. 2 1,0 SYMBOL H DS1,0 NAME DESCRIPTION Head Address The current head address. Drive Select The current selected drive. Table 8.18 - Status Register 1 BIT NO. 7 SYMBOL EN NAME End of Cylinder DESCRIPTION The FDC tried to access a sector beyond the final sector of the track (255D). Will be set if TC is not issued after Read or Write Data command. Unused. This bit is always "0". The FDC detected a CRC error in either the ID field or the data field of a sector. Becomes set if the FDC does not receive CPU or DMA service within the required time interval, resulting in data overrun or underrun. Unused. This bit is always "0". Any one of the following: 1. Read Data, Read Deleted Data command - the FDC did not find the specified sector. 2. Read ID command - the FDC cannot read the ID field without an error. 3. Read A Track command - the FDC cannot find the proper sector sequence. WP pin became a "1" while the FDC is executing a Write Data, Write Deleted Data, or Format A Track command. Any one of the following: 1. The FDC did not detect an ID address mark at the specified track after encountering the index pulse from the nINDEX pin twice. 2. The FDC cannot detect a data address mark or a deleted data address mark on the specified track. 6 5 4 DE OR Data Error Overrun/ Underrun 3 2 ND No Data 1 0 NW MA Not Writeable Missing Address Mark Table 8.19 - Status Register 2 BIT NO. 7 6 SYMBOL CM NAME Control Mark DESCRIPTION Unused. This bit is always "0". Any one of the following: Read Data command - the FDC encountered a deleted data address mark. Read Deleted Data command - the FDC encountered a data address mark. The FDC detected a CRC error in the data field. The track address from the sector ID field is different from the track address maintained inside the FDC. Unused. This bit is always "0". Unused. This bit is always "0". 5 4 3 2 DD WC Data Error in Data Field Wrong Cylinder SMSC SIO10N268 Page 65 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet BIT NO. 1 SYMBOL BC NAME Bad Cylinder 0 MD Missing Data Address Mark DESCRIPTION The track address from the sector ID field is different from the track address maintained inside the FDC and is equal to FF hex, which indicates a bad track with a hard error according to the IBM soft-sectored format. The FDC cannot detect a data address mark or a deleted data address mark. Table 8.20 - Status Register 3 BIT NO. 7 6 5 4 3 2 1,0 SYMBOL WP NAME Write Protected DESCRIPTION Unused. This bit is always "0". Indicates the status of the WRTPRT pin. T0 HD DS1,0 Unused. This bit is always "1". Track 0 Indicates the status of the TRK0 pin. Unused. This bit is always "1". Head Address Indicates the status of the HDSEL pin. Drive Select Indicates the status of the DS1, DS0 pins. 8.7.2.1 Reset There are three sources of system reset on the FDC: the PCI_RESET# pin, a reset generated via a bit in the DOR, and a reset generated via a bit in the DSR. At power on, a Power On Reset initializes the FDC. All resets take the FDC out of the power down state. All operations are terminated upon a PCI_RESET#, and the FDC enters an idle state. A reset while a disk write is in progress will corrupt the data and CRC. On exiting the reset state, various internal registers are cleared, including the Configure command information, and the FDC waits for a new command. Drive polling will start unless disabled by a new Configure command. PCI_RESET# Pin (Hardware Reset) The PCI_RESET# pin is a global reset and clears all registers except those programmed by the Specify command. The DOR reset bit is enabled and must be cleared by the host to exit the reset state. DOR Reset vs. DSR Reset (Software Reset) These two resets are functionally the same. Both will reset the FDC core, which affects drive status information and the FIFO circuits. The DSR reset clears itself automatically while the DOR reset requires the host to manually clear it. DOR reset has precedence over the DSR reset. The DOR reset is set automatically upon a pin reset. The user must manually clear this reset bit in the DOR to exit the reset state. 8.7.2.2 Modes Of Operation The FDC has three modes of operation, PC/AT mode, PS/2 mode and Model 30 mode. These are determined by the state of the Interface Mode bits (MFM and IDENT) in CR03[5,6]. Rev. 0.5 (03-24-05) Page 66 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet PC/AT mode The PC/AT register set is enabled, the DMA enable bit of the DOR becomes valid (controls the interrupt and DMA functions), and DENSEL is an active high signal. PS/2 mode This mode supports the PS/2 models 50/60/80 configuration and register set. The DMA bit of the DOR becomes a "don't care". The DMA and interrupt functions are always enabled, and DENSEL is active low. Model 30 mode This mode supports PS/2 Model 30 configuration and register set. The DMA enable bit of the DOR becomes valid (controls the interrupt and DMA functions), and DENSEL is active low. 8.7.3 DMA Transfers DMA transfers are enabled with the Specify command and are initiated by the FDC by activating a DMA request cycle. DMA read, write and verify cycles are supported. The FDC supports two DMA transfer modes: single Transfer and Burst Transfer. Burst mode is enabled via CR05-Bit[2]. See the Configuration section. 8.7.4 Controller Phases For simplicity, command handling in the FDC can be divided into three phases: Command, Execution, and Result. Each phase is described in the following sections. 8.7.4.1 Command Phase After a reset, the FDC enters the command phase and is ready to accept a command from the host. For each of the commands, a defined set of command code bytes and parameter bytes has to be written to the FDC before the command phase is complete. (Please refer to Table 8.21 for the command set descriptions). These bytes of data must be transferred in the order prescribed. Before writing to the FDC, the host must examine the RQM and DIO bits of the Main Status Register. RQM and DIO must be equal to "1" and "0" respectively before command bytes may be written. RQM is set false by the FDC after each write cycle until the received byte is processed. The FDC asserts RQM again to request each parameter byte of the command unless an illegal command condition is detected. After the last parameter byte is received, RQM remains "0" and the FDC automatically enters the next phase as defined by the command definition. The FIFO is disabled during the command phase to provide for the proper handling of the "Invalid Command" condition. 8.7.4.2 Execution Phase All data transfers to or from the FDC occur during the execution phase, which can proceed in DMA or nonDMA mode as indicated in the Specify command. After a reset, the FIFO is disabled. Each data byte is transferred by a read/write or DMA cycle depending on the DMA mode. The Configure command can enable the FIFO and set the FIFO threshold value. SMSC SIO10N268 Page 67 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet The following paragraphs detail the operation of the FIFO flow control. In these descriptions, 8.7.4.3 Data Transfer Termination The FDC supports terminal count explicitly through the TC cycle and implicitly through the underrun/overrun and end-of-track (EOT) functions. For full sector transfers, the EOT parameter can define the last sector to be transferred in a single or multi-sector transfer. If the last sector to be transferred is a partial sector, the host can stop transferring the data in mid-sector, and the FDC will continue to complete the sector as if a TC cycle was received. The only difference between these implicit functions and TC cycle is that they return "abnormal termination" result status. Such status indications can be ignored if they were expected. NOTE: When the host is sending data to the FIFO of the FDC, the internal sector count will be complete when the FDC reads the last byte from its side of the FIFO. There may be a delay in the removal of the transfer request signal of up to the time taken for the FDC to read the last 16 bytes from the FIFO. The host must tolerate this delay. 8.7.4.4 Result Phase The generation of the interrupt determines the beginning of the result phase. For each of the commands, a defined set of result bytes has to be read from the FDC before the result phase is complete. These bytes of data must be read out for another command to start. Rev. 0.5 (03-24-05) Page 68 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet RQM and DIO must both equal "1" before the result bytes may be read. After all the result bytes have been read, the RQM and DIO bits switch to "1" and "0" respectively, and the CB bit is cleared, indicating that the FDC is ready to accept the next command. 8.7.5 Command Set/Descriptions Commands can be written whenever the FDC is in the command phase. Each command has a unique set of needed parameters and status results. The FDC checks to see that the first byte is a valid command and, if valid, proceeds with the command. If it is invalid, an interrupt is issued. The user sends a Sense Interrupt Status command which returns an invalid command error. Refer to Table 8.21 for explanations of the various symbols used. Table 8.22 lists the required parameters and the results associated with each command that the FDC is capable of performing. Table 8.21 - Description of Command Symbols SYMBOL C D D0, D1 DESCRIPTION The currently selected address; 0 to 255. The pattern to be written in each sector data field during formatting. Designates which drives are perpendicular drives on the Perpendicular Mode Command. A "1" indicates a perpendicular drive. Direction Control If this bit is 0, then the head will step out from the spindle during a relative seek. If set to a 1, the head will step in toward the spindle. Disk Drive Select DS1 DS0 DRIVE 0 0 Drive 0 0 1 Drive 1 Special Sector By setting N to zero (00), DTL may be used to control the number of Size bytes transferred in disk read/write commands. The sector size (N = 0) is set to 128. If the actual sector (on the diskette) is larger than DTL, the remainder of the actual sector is read but is not passed to the host during read commands; during write commands, the remainder of the actual sector is written with all zero bytes. The CRC check code is calculated with the actual sector. When N is not zero, DTL has no meaning and should be set to FF HEX. Enable Count When this bit is "1" the "DTL" parameter of the Verify command becomes SC (number of sectors per track). Enable FIFO This active low bit when a 0, enables the FIFO. A "1" disables the FIFO (default). Enable Implied When set, a seek operation will be performed before executing any Seek read or write command that requires the C parameter in the command phase. A "0" disables the implied seek. End of Track The final sector number of the current track. Alters Gap 2 length when using Perpendicular Mode. Gap Length The Gap 3 size. (Gap 3 is the space between sectors excluding the VCO synchronization field). Head Address Selected head: 0 or 1 (disk side 0 or 1) as encoded in the sector ID field. Head Load Time The time interval that FDC waits after loading the head and before initializing a read or write operation. Refer to the Specify command for actual delays. Head Unload Time The time interval from the end of the execution phase (of a read or write command) until the head is unloaded. Refer to the Specify command for actual delays. NAME Cylinder Address Data Pattern Drive Select 0-1 DIR DS0, DS1 DTL EC EFIFO EIS EOT GAP GPL H/HDS HLT HUT SMSC SIO10N268 Page 69 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet SYMBOL LOCK NAME MFM MT MFM/FM Mode Selector Multi-Track Selector N Sector Size Code NCN ND OW PCN POLL PRETRK New Cylinder Number Non-DMA Mode Flag Overwrite Present Cylinder Number Polling Disable Precompensation Start Track Number Sector Address DESCRIPTION Lock defines whether EFIFO, FIFOTHR, and PRETRK parameters of the CONFIGURE COMMAND can be reset to their default values by a "software Reset". (A reset caused by writing to the appropriate bits of either the DSR or DOR) A one selects the double density (MFM) mode. A zero selects single density (FM) mode. When set, this flag selects the multi-track operating mode. In this mode, the FDC treats a complete cylinder under head 0 and 1 as a single track. The FDC operates as this expanded track started at the first sector under head 0 and ended at the last sector under head 1. With this flag set, a multitrack read or write operation will automatically continue to the first sector under head 1 when the FDC finishes operating on the last sector under head 0. This specifies the number of bytes in a sector. If this parameter is "00", then the sector size is 128 bytes. The number of bytes transferred is determined by the DTL parameter. Otherwise the sector size is (2 raised to the "N'th" power) times 128. All values up to "07" hex are allowable. "07"h would equal a sector size of 16k. It is the user's responsibility to not select combinations that are not possible with the drive. N SECTOR SIZE 00 128 Bytes 01 256 Bytes 02 512 Bytes 03 1024 Bytes ... ... 07 16K Bytes The desired cylinder number. Write `0'. This part does not support non-DMA mode. The bits D0-D3 of the Perpendicular Mode Command can only be modified if OW is set to 1. OW id defined in the Lock command. The current position of the head at the completion of Sense Interrupt Status command. When set, the internal polling routine is disabled. When clear, polling is enabled. Programmable from track 00 to FFH. R RCN SC SK The sector number to be read or written. In multi-sector transfers, this parameter specifies the sector number of the first sector to be read or written. Relative Cylinder Relative cylinder offset from present cylinder as used by the Relative Number Seek command. Number of Sectors The number of sectors per track to be initialized by the Format Per Track command. The number of sectors per track to be verified during a Verify command when EC is set. Skip Flag When set to 1, sectors containing a deleted data address mark will automatically be skipped during the execution of Read Data. If Read Deleted is executed, only sectors with a deleted address mark will be accessed. When set to "0", the sector is read or written the same as the read and write commands. Rev. 0.5 (03-24-05) Page 70 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet SYMBOL SRT NAME Step Rate Interval ST0 ST1 ST2 ST3 WGATE Status 0 Status 1 Status 2 Status 3 Write Gate DESCRIPTION The time interval between step pulses issued by the FDC. Programmable from 0.5 to 8 milliseconds in increments of 0.5 ms at the 1 Mbit data rate. Refer to the SPECIFY command for actual delays. Registers within the FDC which store status information after a command has been executed. This status information is available to the host during the result phase after command execution. Alters timing of WE to allow for pre-erase loads in perpendicular drives. 8.7.6 Instruction Set Table 8.22 - Instruction Set READ DATA PHASE Command R/W W W W W W W W W W Execution Result R R R R R R R D7 MT 0 D6 MFM 0 D5 SK 0 DATA BUS D4 D3 D2 D1 D0 REMARKS 0 0 1 1 0 Command Codes 0 0 HDS DS1 DS0 C Sector ID information prior to Command execution. H R N EOT GPL DTL Data transfer between the FDD and system. ST0 Status information after Command execution. ST1 ST2 C Sector ID information after Command execution. H R N SMSC SIO10N268 Page 71 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet READ DELETED DATA PHASE Command R/W W W W W W W W W W Execution Result R R R R R R R D7 MT 0 D6 MFM 0 DATA BUS D5 D4 D3 D2 D1 D0 REMARKS SK 0 1 1 0 0 Command Codes 0 0 0 HDS DS1 DS0 C Sector ID information prior to Command execution. H R N EOT GPL DTL Data transfer between the FDD and system. ST0 Status information after Command execution. ST1 ST2 C Sector ID information after Command execution. H R N WRITE DATA PHASE Command R/W W W W W W W W W W Execution Result R R R R R R R D7 MT 0 D6 MFM 0 DATA BUS D5 D4 D3 D2 D1 D0 REMARKS 0 0 0 1 0 1 Command Codes 0 0 0 HDS DS1 DS0 C Sector ID information prior to Command execution. H R N EOT GPL DTL Data transfer between the FDD and system. ST0 Status information after Command execution. ST1 ST2 C Sector ID information after Command execution. H R N Rev. 0.5 (03-24-05) Page 72 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet WRITE DELETED DATA PHASE Command R/W W W W D7 MT 0 D6 MFM 0 D5 0 0 DATA BUS D4 D3 D2 0 1 0 0 0 HDS C D1 0 DS1 D0 1 DS0 REMARKS Command Codes Sector ID information prior to Command execution. W W W W W W Execution Result R R R R H R N EOT GPL DTL Data transfer between the FDD and system. Status information after Command execution. ST0 ST1 ST2 C Sector ID information after Command execution. R R R H R N SMSC SIO10N268 Page 73 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet READ A TRACK PHASE Command R/W W W W D7 0 0 D6 MFM 0 D5 0 0 DATA BUS D4 D3 D2 0 0 0 0 0 HDS C D1 1 DS1 D0 0 DS0 REMARKS Command Codes Sector ID information prior to Command execution. W W W W W W Execution H R N EOT GPL DTL Data transfer between the FDD and system. FDC reads all of cylinders' contents from index hole to EOT. Status information after Command execution. Result R R R R ST0 ST1 ST2 C Sector ID information after Command execution. R R R H R N Rev. 0.5 (03-24-05) Page 74 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet VERIFY PHASE Command R/W W W W D7 MT EC D6 MFM 0 D5 SK 0 DATA BUS D4 D3 D2 1 0 1 0 0 HDS C D1 1 DS1 D0 0 DS0 REMARKS Command Codes Sector ID information prior to Command execution. W W W W W W Execution Result R R R R H R N EOT GPL DTL/SC No data transfer takes place. Status information after Command execution. ST0 ST1 ST2 C Sector ID information after Command execution. R R R H R N VERSION PHASE Command Result R/W W R D7 0 1 D6 0 0 D5 0 0 DATA BUS D4 D3 D2 1 0 0 1 0 0 D1 0 0 D0 0 0 REMARKS Command Code Enhanced Controller FORMAT A TRACK DATA BUS PHASE Command R/W W W W W W W D7 0 0 D6 MFM 0 D5 0 0 D4 0 0 N SC GPL D D3 1 0 D2 1 HDS D1 0 DS1 D0 1 DS0 Bytes/Sector Sectors/Cylinder Gap 3 Filler Byte REMARKS Command Codes Execution for W C Input Sector Parameters SMSC SIO10N268 Page 75 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet FORMAT A TRACK DATA BUS PHASE Each Sector Repeat: W W W H R N FDC formats an entire cylinder Result R ST0 Status information after Command execution R R R R R R ST1 ST2 Undefined Undefined Undefined Undefined RECALIBRATE PHASE Command Execution R/W W W D7 0 0 D6 0 0 D5 0 0 DATA BUS D4 D3 D2 0 0 1 0 0 0 D1 1 DS1 D0 1 DS0 REMARKS Command Codes Head retracted to Track 0 Interrupt. SENSE INTERRUPT STATUS PHASE Command Result R/W W R R D7 0 D6 0 D5 0 DATA BUS D4 D3 D2 0 1 0 ST0 PCN SPECIFY PHASE Command R/W W W W D7 0 DATA BUS D6 D5 D4 D3 D2 D1 0 0 0 0 0 1 SRT HUT HLT D0 1 ND REMARKS Command Codes D1 0 D0 0 REMARKS Command Codes Status information at the end of each seek operation. R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS Rev. 0.5 (03-24-05) Page 76 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet SENSE DRIVE STATUS PHASE Command Result R/W W W R D7 0 0 D6 0 0 D5 0 0 DATA BUS D4 D3 D2 0 0 1 0 0 HDS ST3 D1 0 DS1 D0 0 DS0 REMARKS Command Codes Status information about FDD PHASE Command Execution R/W W W W D7 0 0 D6 0 0 D5 0 0 SEEK DATA BUS D4 D3 D2 0 1 1 0 0 HDS NCN D1 1 DS1 D0 1 DS0 REMARKS Command Codes Head positioned over proper cylinder on diskette. PHASE Command R/W W W W W D7 0 0 0 D6 0 D5 0 CONFIGURE DATA BUS D4 D3 D2 1 0 0 0 0 POLL PRETRK D1 1 D0 1 0 REMARKS Configure Information 0 0 EIS EFIFO 0 0 FIFOTHR Execution PHASE Command R/W W W W D7 1 0 D6 DIR 0 D5 0 0 RELATIVE SEEK DATA BUS D4 D3 D2 D1 0 1 1 1 0 0 HDS DS1 RCN DUMPREG DATA BUS D4 D3 D2 0 1 1 D0 1 DS0 REMARKS PHASE Command R/W W D7 0 D6 0 D5 0 D1 1 D0 0 REMARKS *Note: Registers placed in FIFO Execution Result R R R R R R R R R R PCN-Drive 0 PCN-Drive 1 PCN-Drive 2 PCN-Drive 3 SRT LOCK 0 HLT SC/EOT 0 D3 D2 D1 EIS EFIFO POLL PRETRK D0 HUT ND GAP WGATE FIFOTHR SMSC SIO10N268 Page 77 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet PHASE Command Execution R/W W W D7 0 0 D6 MFM 0 D5 0 0 READ ID DATA BUS D4 D3 D2 0 1 0 0 0 HDS D1 1 DS1 D0 0 DS0 REMARKS Commands The first correct ID information on the Cylinder is stored in Data Register Status information after Command execution. Result R ST0 Disk status after the Command has completed R R R R R R ST1 ST2 C H R N PHASE Command R/W W D7 0 OW D6 0 0 PERPENDICULAR MODE DATA BUS D5 D4 D3 D2 D1 0 1 0 0 1 D3 D2 D1 D0 GAP INVALID CODES DATA BUS D5 D4 D3 D2 D1 Invalid Codes ST0 LOCK DATA BUS D5 D4 D3 0 1 0 0 LOCK 0 D0 REMARKS 0 Command Codes WGATE PHASE Command Result R/W W R D7 D6 D0 REMARKS Invalid Command Codes (NoOp - FDC goes into Standby State) ST0 = 80H PHASE Command Result R/W W R D7 LOCK 0 D6 0 0 D2 1 0 D1 0 0 D0 0 0 REMARKS Command Codes SC is returned if the last command that was issued was the Format command. EOT is returned if the last command was a Read or Write. Note 8.11 These bits are used internally only. They are not reflected in the Drive Select pins. It is the user's responsibility to maintain correspondence between these bits and the Drive Select pins (DOR). Rev. 0.5 (03-24-05) Page 78 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet 8.7.7 Data Transfer Commands All of the Read Data, Write Data and Verify type commands use the same parameter bytes and return the same results information, the only difference being the coding of bits 0-4 in the first byte. An implied seek will be executed if the feature was enabled by the Configure command. This seek is completely transparent to the user. The Drive Busy bit for the drive will go active in the Main Status Register during the seek portion of the command. If the seek portion fails, it is reflected in the results status normally returned for a Read/Write Data command. Status Register 0 (ST0) would contain the error code and C would contain the cylinder on which the seek failed. 8.7.7.1 Read Data A set of nine (9) bytes is required to place the FDC in the Read Data Mode. After the Read Data command has been issued, the FDC loads the head (if it is in the unloaded state), waits the specified head settling time (defined in the Specify command), and begins reading ID Address Marks and ID fields. When the sector address read off the diskette matches with the sector address specified in the command, the FDC reads the sector's data field and transfers the data to the FIFO. After completion of the read operation from the current sector, the sector address is incremented by one and the data from the next logical sector is read and output via the FIFO. This continuous read function is called "Multi-Sector Read Operation". Upon receipt of the TC cycle, or an implied TC (FIFO overrun/underrun), the FDC stops sending data but will continue to read data from the current sector, check the CRC bytes, and at the end of the sector, terminate the Read Data Command. N determines the number of bytes per sector (see Table 8.23 below). If N is set to zero, the sector size is set to 128. The DTL value determines the number of bytes to be transferred. If DTL is less than 128, the FDC transfers the specified number of bytes to the host. For reads, it continues to read the entire 128-byte sector and checks for CRC errors. For writes, it completes the 128-byte sector by filling in zeros. If N is not set to 00 Hex, DTL should be set to FF Hex and has no impact on the number of bytes transferred. Table 8.23 - Sector Sizes N 00 01 02 03 .. 07 SECTOR SIZE 128 bytes 256 bytes 512 bytes 1024 bytes ... 16 Kbytes The amount of data which can be handled with a single command to the FDC depends upon MT (multitrack) and N (number of bytes/sector). The Multi-Track function (MT) allows the FDC to read data from both sides of the diskette. For a particular cylinder, data will be transferred starting at Sector 1, Side 0 and completing the last sector of the same track at Side 1. If the host terminates a read or write operation in the FDC, the ID information in the result phase is dependent upon the state of the MT bit and EOT byte. Refer to Table 8.24. At the completion of the Read Data command, the head is not unloaded until after the Head Unload Time Interval (specified in the Specify command) has elapsed. If the host issues another command before the head unloads, then the head settling time may be saved between subsequent reads. SMSC SIO10N268 Page 79 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet If the FDC detects a pulse on the nINDEX pin twice without finding the specified sector (meaning that the diskette's index hole passes through index detect logic in the drive twice), the FDC sets the IC code in Status Register 0 to "01" indicating abnormal termination, sets the ND bit in Status Register 1 to "1" indicating a sector not found, and terminates the Read Data Command. After reading the ID and Data Fields in each sector, the FDC checks the CRC bytes. If a CRC error occurs in the ID or data field, the FDC sets the IC code in Status Register 0 to "01" indicating abnormal termination, sets the DE bit flag in Status Register 1 to "1", sets the DD bit in Status Register 2 to "1" if CRC is incorrect in the ID field, and terminates the Read Data Command. Table 8.25 describes the effect of the SK bit on the Read Data command execution and results. Except where noted in Table 8.25, the C or R value of the sector address is automatically incremented (see Table 8.27). Table 8.24 - Effects of MT and N Bits MT 0 1 0 1 0 1 N 1 1 2 2 3 3 MAXIMUM TRANSFER CAPACITY 256 x 26 = 6,656 256 x 52 = 13,312 512 x 15 = 7,680 512 x 30 = 15,360 1024 x 8 = 8,192 1024 x 16 = 16,384 FINAL SECTOR READ FROM DISK 26 at side 0 or 1 26 at side 1 15 at side 0 or 1 15 at side 1 8 at side 0 or 1 16 at side 1 Table 8.25 - Skip Bit vs Read Data command SK BIT VALUE DATA ADDRESS MARK TYPE ENCOUNTERED SECTOR READ? Yes Yes RESULTS CM BIT OF ST2 SET? No Yes DESCRIPTION OF RESULTS Normal termination. Address not incremented. Next sector not searched for. Normal termination. Normal termination. Sector not read ("skipped"). 0 0 Normal Data Deleted Data 1 1 Normal Data Deleted Data Yes No No Yes 8.7.7.2 Read Deleted Data This command is the same as the Read Data command, only it operates on sectors that contain a Deleted Data Address Mark at the beginning of a Data Field. Table 8.26 describes the effect of the SK bit on the Read Deleted Data command execution and results. Except where noted in Table 8.26, the C or R value of the sector address is automatically incremented (see Table 8.27). Rev. 0.5 (03-24-05) Page 80 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet Table 8.26 - Skip Bit vs. Read Deleted Data Command SK BIT VALUE DATA ADDRESS MARK TYPE ENCOUNTERED SECTOR READ? Yes RESULTS CM BIT OF ST2 SET? Yes DESCRIPTION OF RESULTS Address not incremented. Next sector not searched for. Normal termination. Normal termination. Sector not read ("skipped"). Normal termination. 0 Normal Data 0 1 Deleted Data Normal Data Yes No No Yes 1 Deleted Data Yes No 8.7.7.3 Read A Track This command is similar to the Read Data command except that the entire data field is read continuously from each of the sectors of a track. Immediately after encountering a pulse on the nINDEX pin, the FDC starts to read all data fields on the track as continuous blocks of data without regard to logical sector numbers. If the FDC finds an error in the ID or DATA CRC check bytes, it continues to read data from the track and sets the appropriate error bits at the end of the command. The FDC compares the ID information read from each sector with the specified value in the command and sets the ND flag of Status Register 1 to a "1" if there no comparison. Multi-track or skip operations are not allowed with this command. The MT and SK bits (bits D7 and D5 of the first command byte respectively) should always be set to "0". This command terminates when the EOT specified number of sectors has not been read. If the FDC does not find an ID Address Mark on the diskette after the second occurrence of a pulse on the nINDEX pin, then it sets the IC code in Status Register 0 to "01" (abnormal termination), sets the MA bit in Status Register 1 to "1", and terminates the command. Table 8.27 - Result Phase Table MT 0 HEAD 0 1 1 0 1 FINAL SECTOR TRANSFERRED TO HOST Less than EOT Equal to EOT Less than EOT Equal to EOT Less than EOT Equal to EOT Less than EOT Equal to EOT ID INFORMATION AT RESULT PHASE C H R N NC NC R+1 NC C+1 NC 01 NC NC NC R+1 NC C+1 NC 01 NC NC NC R+1 NC NC LSB 01 NC NC NC R+1 NC C+1 LSB 01 NC NC: No Change, the same value as the one at the beginning of command execution. SMSC SIO10N268 Page 81 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet LSB: Least Significant Bit, the LSB of H is complemented. 8.7.7.4 Write Data After the Write Data command has been issued, the FDC loads the head (if it is in the unloaded state), waits the specified head load time if unloaded (defined in the Specify command), and begins reading ID fields. When the sector address read from the diskette matches the sector address specified in the command, the FDC reads the data from the host via the FIFO and writes it to the sector's data field. After writing data into the current sector, the FDC computes the CRC value and writes it into the CRC field at the end of the sector transfer. The Sector Number stored in "R" is incremented by one, and the FDC continues writing to the next data field. The FDC continues this "Multi-Sector Write Operation". Upon receipt of a terminal count signal or if a FIFO over/under run occurs while a data field is being written, then the remainder of the data field is filled with zeros. The FDC reads the ID field of each sector and checks the CRC bytes. If it detects a CRC error in one of the ID fields, it sets the IC code in Status Register 0 to "01" (abnormal termination), sets the DE bit of Status Register 1 to "1", and terminates the Write Data command. The Write Data command operates in much the same manner as the Read Data command. The following items are the same. Please refer to the Read Data Command for details: Transfer Capacity EN (End of Cylinder) bit ND (No Data) bit Head Load, Unload Time Interval ID information when the host terminates the command Definition of DTL when N = 0 and when N does not = 0 8.7.7.5 Write Deleted Data This command is almost the same as the Write Data command except that a Deleted Data Address Mark is written at the beginning of the Data Field instead of the normal Data Address Mark. This command is typically used to mark a bad sector containing an error on the floppy disk. 8.7.7.6 Verify The Verify command is used to verify the data stored on a disk. This command acts exactly like a Read Data command except that no data is transferred to the host. Data is read from the disk and CRC is computed and checked against the previously-stored value. Because data is not transferred to the host, the TC cycle cannot be used to terminate this command. By setting the EC bit to "1", an implicit TC will be issued to the FDC. This implicit TC will occur when the SC value has decremented to 0 (an SC value of 0 will verify 256 sectors). This command can also be terminated by setting the EC bit to "0" and the EOT value equal to the final sector to be checked. If EC is set to "0", DTL/SC should be programmed to 0FFH. Refer to Table 8.27 and Table 8.28 for information concerning the values of MT and EC versus SC and EOT value. Definitions: # Sectors Per Side = Number of formatted sectors per each side of the disk. # Sectors Remaining = Number of formatted sectors left which can be read, including side 1 of the disk if MT is set to "1". Rev. 0.5 (03-24-05) Page 82 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet Table 8.28 - Verify Command Result Phase Table MT 0 0 0 0 1 1 1 1 EC 0 0 1 1 0 0 1 1 SC/EOT VALUE SC = DTL EOT <= # Sectors Per Side SC = DTL EOT > # Sectors Per Side SC <= # Sectors Remaining AND EOT <= # Sectors Per Side SC > # Sectors Remaining OR EOT > # Sectors Per Side SC = DTL EOT <= # Sectors Per Side SC = DTL EOT > # Sectors Per Side SC <= # Sectors Remaining AND EOT <= # Sectors Per Side SC > # Sectors Remaining OR EOT > # Sectors Per Side Note 8.12 TERMINATION RESULT Success Termination Result Phase Valid Unsuccessful Termination Result Phase Invalid Successful Termination Result Phase Valid Unsuccessful Termination Result Phase Invalid Successful Termination Result Phase Valid Unsuccessful Termination Result Phase Invalid Successful Termination Result Phase Valid Unsuccessful Termination Result Phase Invalid If MT is set to "1" and the SC value is greater than the number of remaining formatted sectors on Side 0, verifying will continue on Side 1 of the disk. 8.7.7.7 Format A Track The Format command allows an entire track to be formatted. After a pulse from the nINDEX pin is detected, the FDC starts writing data on the disk including gaps, address marks, ID fields, and data fields per the IBM System 34 or 3740 format (MFM or FM respectively). The particular values that will be written to the gap and data field are controlled by the values programmed into N, SC, GPL, and D which are specified by the host during the command phase. The data field of the sector is filled with the data byte specified by D. The ID field for each sector is supplied by the host; that is, four data bytes per sector are needed by the FDC for C, H, R, and N (cylinder, head, sector number and sector size respectively). After formatting each sector, the host must send new values for C, H, R and N to the FDC for the next sector on the track. The R value (sector number) is the only value that must be changed by the host after each sector is formatted. This allows the disk to be formatted with nonsequential sector addresses (interleaving). This incrementing and formatting continues for the whole track until the FDC encounters a pulse on the nINDEX pin again and it terminates the command. Table 8.29 contains typical values for gap fields which are dependent upon the size of the sector and the number of sectors on each track. Actual values can vary due to drive electronics. SMSC SIO10N268 Page 83 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet FORMAT FIELDS SYSTEM 34 (DOUBLE DENSITY) FORMAT GAP4a 80x 4E SYNC 12x 00 IAM GAP1 SYNC 50x 12x 4E 00 IDAM C Y L H D S N C GAP2 SYNC EOR 22x 12x C C 4E 00 DATA AM C DATA R GAP3 GAP 4b C 3x FC C2 3x FE A1 3x FB A1 F8 DATA AM SYSTEM 3740 (SINGLE DENSITY) FORMAT GAP4a 40x FF SYNC 6x 00 IAM GAP1 SYNC 26x 6x FF 00 IDAM C Y L H D S N C GAP2 SYNC EOR 11x 6x C C FF 00 C DATA R GAP3 GAP 4b C FC FE FB or F8 DATA AM PERPENDICULAR FORMAT GAP4a 80x 4E SYNC 12x 00 IAM GAP1 SYNC 50x 12x 4E 00 IDAM C Y L H D S N C GAP2 SYNC EOR 41x 12x C C 4E 00 C DATA R GAP3 GAP 4b C 3x FC C2 3x FE A1 3x FB A1 F8 Table 8.29 - Typical Values for Formatting SECTOR SIZE N SC GPL1 GPL2 128 00 12 07 09 128 00 10 10 19 512 02 08 18 30 FM 1024 03 04 46 87 2048 04 02 C8 FF 4096 05 01 C8 FF 5.25" Drives ... ... 256 01 12 0A 0C 256 01 10 20 32 512* 02 09 2A 50 MFM 1024 03 04 80 F0 2048 04 02 C8 FF 4096 05 01 C8 FF ... ... 128 0 0F 07 1B FM 256 1 09 0F 2A 3.5" Drives 512 2 05 1B 3A 256 1 0F 0E 36 MFM 512** 2 09 1B 54 1024 3 05 35 74 GPL1 = suggested GPL values in Read and Write commands to avoid splice point between data field and ID field of contiguous sections. GPL2 = suggested GPL value in Format A Track command. *PC/AT values (typical) **PS/2 values (typical). Applies with 1.0 MB and 2.0 MB drives. Note 8.13 All values except sector size are in hex. FORMAT Rev. 0.5 (03-24-05) Page 84 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet 8.7.8 Control Commands Control commands differ from the other commands in that no data transfer takes place. Three commands generate an interrupt when complete: Read ID, Recalibrate, and Seek. The other control commands do not generate an interrupt. 8.7.8.1 Read ID The Read ID command is used to find the present position of the recording heads. The FDC stores the values from the first ID field it is able to read into its registers. If the FDC does not find an ID address mark on the diskette after the second occurrence of a pulse on the nINDEX pin, it then sets the IC code in Status Register 0 to "01" (abnormal termination), sets the MA bit in Status Register 1 to "1", and terminates the command. The following commands will generate an interrupt upon completion. They do not return any result bytes. It is highly recommended that control commands be followed by the Sense Interrupt Status command. Otherwise, valuable interrupt status information will be lost. 8.7.8.2 Recalibrate This command causes the read/write head within the FDC to retract to the track 0 position. The FDC clears the contents of the PCN counter and checks the status of the nTRK0 pin from the FDD. As long as the nTRK0 pin is low, the DIR pin remains 0 and step pulses are issued. When the nTRK0 pin goes high, the SE bit in Status Register 0 is set to "1" and the command is terminated. If the nTR0 pin is still low after 255 step pulses have been issued, the FDC sets the SE and the EC bits of Status Register 0 to "1" and terminates the command. Disks capable of handling more than 255 tracks per side may require more than one Recalibrate command to return the head back to physical Track 0. The Recalibrate command does not have a result phase. The Sense Interrupt Status command must be issued after the Recalibrate command to effectively terminate it and to provide verification of the head position (PCN). During the command phase of the recalibrate operation, the FDC is in the BUSY state, but during the execution phase it is in a NON-BUSY state. At this time, another Recalibrate command may be issued, and in this manner parallel Recalibrate operations may be done on up to four drives at once. Upon power up, the software must issue a Recalibrate command to properly initialize all drives and the controller. 8.7.8.3 Seek The read/write head within the drive is moved from track to track under the control of the Seek command. The FDC compares the PCN, which is the current head position, with the NCN and performs the following operation if there is a difference: PCN < NCN: PCN > NCN: Direction signal to drive set to "1" (step in) and issues step pulses. Direction signal to drive set to "0" (step out) and issues step pulses. The rate at which step pulses are issued is controlled by SRT (Stepping Rate Time) in the Specify command. After each step pulse is issued, NCN is compared against PCN, and when NCN = PCN the SE bit in Status Register 0 is set to "1" and the command is terminated. During the command phase of the seek or recalibrate operation, the FDC is in the BUSY state, but during the execution phase it is in the NON-BUSY state. At this time, another Seek or Recalibrate command may be issued, and in this manner, parallel seek operations may be done on up to four drives at once. SMSC SIO10N268 Page 85 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet NOTE: If implied seek is not enabled, the read and write commands should be preceded by: 1) 2) 3) 4) Seek command - Step to the proper track Sense Interrupt Status command - Terminate the Seek command Read ID - Verify head is on proper track Issue Read/Write command. The Seek command does not have a result phase. Therefore, it is highly recommended that the Sense Interrupt Status command is issued after the Seek command to terminate it and to provide verification of the head position (PCN). The H bit (Head Address) in ST0 will always return to a "0". When exiting POWERDOWN mode, the FDC clears the PCN value and the status information to zero. Prior to issuing the POWERDOWN command, it is highly recommended that the user service all pending interrupts through the Sense Interrupt Status command. 8.7.8.4 Sense Interrupt Status An interrupt signal is generated by the FDC for one of the following reasons: 1) Upon entering the Result Phase of: 1) 2) 3) 4) 5) 6) 7) 8) Read Data command Read A Track command Read ID command Read Deleted Data command Write Data command Format A Track command Write Deleted Data command Verify command 2) End of Seek, Relative Seek, or Recalibrate command The Sense Interrupt Status command resets the interrupt signal and, via the IC code and SE bit of Status Register 0, identifies the cause of the interrupt. Table 8.30 - Interrupt Identification SE 0 1 IC 11 00 INTERRUPT DUE TO Polling Normal termination of Seek or Recalibrate command Abnormal termination of Seek or Recalibrate command 1 01 The Seek, Relative Seek, and Recalibrate commands have no result phase. The Sense Interrupt Status command must be issued immediately after these commands to terminate them and to provide verification of the head position (PCN). The H (Head Address) bit in ST0 will always return a "0". If a Sense Interrupt Status is not issued, the drive will continue to be BUSY and may affect the operation of the next command. Rev. 0.5 (03-24-05) Page 86 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet 8.7.8.5 Sense Drive Status Sense Drive Status obtains drive status information. It has not execution phase and goes directly to the result phase from the command phase. Status Register 3 contains the drive status information. 8.7.8.6 Specify The Specify command sets the initial values for each of the three internal times. The HUT (Head Unload Time) defines the time from the end of the execution phase of one of the read/write commands to the head unload state. The SRT (Step Rate Time) defines the time interval between adjacent step pulses. Note that the spacing between the first and second step pulses may be shorter than the remaining step pulses. The HLT (Head Load Time) defines the time between when the Head Load signal goes high and the read/write operation starts. The values change with the data rate speed selection and are documented in Table 8.31. The values are the same for MFM and FM. DMA operation is selected by the ND bit. When ND is "0", the DMA mode is selected. In DMA mode, data transfers are signaled by the DMA request cycles. 8.7.8.7 Configure The Configure command is issued to select the special features of the FDC. A Configure command need not be issued if the default values of the FDC meet the system requirements. Table 8.31 - Drive Control Delays (ms) 2M 64 4 .. 56 60 1M 128 8 .. 112 120 HUT 500K 300K 256 426 16 26.7 .. .. 224 373 240 400 250K 512 32 .. 448 480 2M 4 3.75 .. 0.5 0.25 HLT 00 01 02 .. 7F 7F 2M 64 0.5 1 .. 63 63.5 1M 128 1 2 .. 126 127 500K 256 2 4 .. 252 254 300K 426 3.3 6.7 .. 420 423 250K 512 4 8 . 504 508 1M 8 7.5 .. 1 0.5 SRT 500K 300K 16 26.7 15 25 .. .. 2 3.33 1 1.67 250K 32 30 .. 4 2 0 1 .. E F Configure Default Values: EIS - No Implied Seeks EFIFO - FIFO Disabled POLL - Polling Enabled FIFOTHR - FIFO Threshold Set to 1 Byte PRETRK - Pre-Compensation Set to Track 0 EIS - Enable Implied Seek. When set to "1", the FDC will perform a Seek operation before executing a read or write command. Defaults to no implied seek. SMSC SIO10N268 Page 87 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet EFIFO - A "1" disables the FIFO (default). This means data transfers are asked for on a byte-by-byte basis. Defaults to "1", FIFO disabled. The threshold defaults to "1". POLL - Disable polling of the drives. Defaults to "0", polling enabled. When enabled, a single interrupt is generated after a reset. No polling is performed while the drive head is loaded and the head unload delay has not expired. FIFOTHR - The FIFO threshold in the execution phase of read or write commands. This is programmable from 1 to 16 bytes. Defaults to one byte. A "00" selects one byte; "0F" selects 16 bytes. PRETRK - Pre-Compensation Start Track Number. Programmable from track 0 to 255. Defaults to track 0. A "00" selects track 0; "FF" selects track 255. 8.7.8.8 Version The Version command checks to see if the controller is an enhanced type or the older type (765A). A value of 90 H is returned as the result byte. 8.7.8.9 Relative Seek The command is coded the same as for Seek, except for the MSB of the first byte and the DIR bit. DIR Head Step Direction Control RCN Relative Cylinder Number that determines how many tracks to step the head in or out from the current track number. DIR 0 1 ACTION Step Head Out Step Head In The Relative Seek command differs from the Seek command in that it steps the head the absolute number of tracks specified in the command instead of making a comparison against an internal register. The Seek command is good for drives that support a maximum of 256 tracks. Relative Seeks cannot be overlapped with other Relative Seeks. Only one Relative Seek can be active at a time. Relative Seeks may be overlapped with Seeks and Recalibrates. Bit 4 of Status Register 0 (EC) will be set if Relative Seek attempts to step outward beyond Track 0. As an example, assume that a floppy drive has 300 useable tracks. The host needs to read track 300 and the head is on any track (0-255). If a Seek command is issued, the head will stop at track 255. If a Relative Seek command is issued, the FDC will move the head the specified number of tracks, regardless of the internal cylinder position register (but will increment the register). If the head was on track 40 (d), the maximum track that the FDC could position the head on using Relative Seek will be 295 (D), the initial track + 255 (D). The maximum count that the head can be moved with a single Relative Seek command is 255 (D). The internal register, PCN, will overflow as the cylinder number crosses track 255 and will contain 39 (D). The resulting PCN value is thus (RCN + PCN) mod 256. Functionally, the FDC starts counting from 0 again as the track number goes above 255 (D). It is the user's responsibility to compensate FDC functions (precompensation track number) when accessing tracks greater than 255. The FDC does not keep track that it is working in an "extended track area" (greater than 255). Any command issued will use the current PCN value except for the Recalibrate command, which only looks for the TRACK0 signal. Recalibrate will return an error if the head is farther than 255 due to its limitation of issuing a maximum of 255 step pulses. The user simply needs to issue a second Recalibrate command. The Seek command and implied seeks will function correctly within the 44 (D) track (299-255) area of the "extended track area". It is the user's responsibility not to issue a new track position that will exceed the maximum track that is present in the extended area. Rev. 0.5 (03-24-05) Page 88 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet To return to the standard floppy range (0-255) of tracks, a Relative Seek should be issued to cross the track 255 boundary. A Relative Seek can be used instead of the normal Seek, but the host is required to calculate the difference between the current head location and the new (target) head location. This may require the host to issue a Read ID command to ensure that the head is physically on the track that software assumes it to be. Different FDC commands will return different cylinder results which may be difficult to keep track of with software without the Read ID command. 8.7.8.10 Perpendicular Mode The Perpendicular Mode command should be issued prior to executing Read/Write/Format commands that access a disk drive with perpendicular recording capability. With this command, the length of the Gap2 field and VCO enable timing can be altered to accommodate the unique requirements of these drives. Table 8.32 describes the effects of the WGATE and GAP bits for the Perpendicular Mode command. Upon a reset, the FDC will default to the conventional mode (WGATE = 0, GAP = 0). Selection of the 500 Kbps and 1 Mbps perpendicular modes is independent of the actual data rate selected in the Data Rate Select Register. The user must ensure that these two data rates remain consistent. The Gap2 and VCO timing requirements for perpendicular recording type drives are dictated by the design of the read/write head. In the design of this head, a pre-erase head precedes the normal read/write head by a distance of 200 micrometers. This works out to about 38 bytes at a 1 Mbps recording density. Whenever the write head is enabled by the Write Gate signal, the pre-erase head is also activated at the same time. Thus, when the write head is initially turned on, flux transitions recorded on the media for the first 38 bytes will not be preconditioned with the pre-erase head since it has not yet been activated. To accommodate this head activation and deactivation time, the Gap2 field is expanded to a length of 41 bytes. The Format Fields table illustrates the change in the Gap2 field size for the perpendicular format. On the read back by the FDC, the controller must begin synchronization at the beginning of the sync field. For the conventional mode, the internal PLL VCO is enabled (VCOEN) approximately 24 bytes from the start of the Gap2 field. But, when the controller operates in the 1 Mbps perpendicular mode (WGATE = 1, GAP = 1), VCOEN goes active after 43 bytes to accommodate the increased Gap2 field size. For both cases, and approximate two-byte cushion is maintained from the beginning of the sync field for the purposes of avoiding write splices in the presence of motor speed variation. For the Write Data case, the FDC activates Write Gate at the beginning of the sync field under the conventional mode. The controller then writes a new sync field, data address mark, data field, and CRC. With the pre-erase head of the perpendicular drive, the write head must be activated in the Gap2 field to insure a proper write of the new sync field. For the 1 Mbps perpendicular mode (WGATE = 1, GAP = 1), 38 bytes will be written in the Gap2 space. Since the bit density is proportional to the data rate, 19 bytes will be written in the Gap2 field for the 500 Kbps perpendicular mode (WGATE = 1, GAP =0). It should be noted that none of the alterations in Gap2 size, VCO timing, or Write Gate timing affect normal program flow. The information provided here is just for background purposes and is not needed for normal operation. Once the Perpendicular Mode command is invoked, FDC software behavior from the user standpoint is unchanged. The perpendicular mode command is enhanced to allow specific drives to be designated Perpendicular recording drives. This enhancement allows data transfers between Conventional and Perpendicular drives without having to issue Perpendicular mode commands between the accesses of the different drive types, nor having to change write pre-compensation values. SMSC SIO10N268 Page 89 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet When both GAP and WGATE bits of the PERPENDICULAR MODE COMMAND are both programmed to "0" (Conventional mode), then D0, D1, D2, D3, and D4 can be programmed independently to "1" for that drive to be set automatically to Perpendicular mode. In this mode the following set of conditions also apply: 1) The GAP2 written to a perpendicular drive during a write operation will depend upon the programmed data rate. The write pre-compensation given to a perpendicular mode drive will be 0ns. For D0-D3 programmed to "0" for conventional mode drives any data written will be at the currently programmed write pre-compensation. 2) 3) NOTE: Bits D0-D3 can only be overwritten when OW is programmed as a "1". If either GAP or WGATE is a "1" then D0-D3 are ignored. Software and hardware resets have the following effect on the PERPENDICULAR MODE COMMAND: 1) "Software" resets (via the DOR or DSR registers) will only clear GAP and WGATE bits to "0". D0-D3 are unaffected and retain their previous value. "Hardware" resets will clear all bits (GAP, WGATE and D0-D3) to "0", i.e all conventional mode. Table 8.32 - Effects of WGATE and GAP Bits LENGTH OF GAP2 FORMAT FIELD 22 Bytes 22 Bytes 22 Bytes 41 Bytes PORTION OF GAP 2 WRITTEN BY WRITE DATA OPERATION 0 Bytes 19 Bytes 0 Bytes 38 Bytes 2) WGATE GAP MODE 0 0 1 1 0 1 0 1 Conventional Perpendicular (500 Kbps) Reserved (Conventional) Perpendicular (1 Mbps) 8.7.8.11 Lock In order to protect systems with long DMA latencies against older application software that can disable the FIFO the LOCK Command has been added. This command should only be used by the FDC routines, and application software should refrain from using it. If an application calls for the FIFO to be disabled then the CONFIGURE command should be used. The LOCK command defines whether the EFIFO, FIFOTHR, and PRETRK parameters of the CONFIGURE command can be RESET by the DOR and DSR registers. When the LOCK bit is set to logic "1" all subsequent "software RESETS by the DOR and DSR registers will not change the previously set parameters to their default values. All "hardware" RESET from the PCI_RESET# pin will set the LOCK bit to logic "0" and return the EFIFO, FIFOTHR, and PRETRK to their default values. A status byte is returned immediately after issuing a LOCK command. This byte reflects the value of the LOCK bit set by the command byte. Rev. 0.5 (03-24-05) Page 90 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet 8.7.8.12 Enhanced DUMPREG The DUMPREG command is designed to support system run-time diagnostics and application software development and debug. To accommodate the LOCK command and the enhanced PERPENDICULAR MODE command the eighth byte of the DUMPREG command has been modified to contain the additional data from these two commands. 8.7.8.13 Compatibility The SIO10N268 was designed with software compatibility in mind. It is a fully backwards- compatible solution with the older generation 765A/B disk controllers. The FDC also implements on-board registers for compatibility with the PS/2, as well as PC/AT and PC/XT, floppy disk controller subsystems. After a hardware reset of the FDC, all registers, functions and enhancements default to a PC/AT, PS/2 or PS/2 Model 30 compatible operating mode, depending on how the IDENT and MFM bits are configured by the system BIOS. 8.8 Serial Port (UART) The SIO10N268 incorporates four full function UARTs. They are compatible with the 16450, the 16450 ACE registers and the 16C550A. The UARTS perform serial-to-parallel conversion on received characters and parallel-to-serial conversion on transmit characters. The data rates are independently programmable from 460.8K baud down to 50 baud. The character options are programmable for 1 start; 1, 1.5 or 2 stop bits; even, odd, sticky or no parity; and prioritized interrupts. The UARTs each contain a programmable baud rate generator that is capable of dividing the input clock or crystal by a number from 1 to 65535. The UARTs are also capable of supporting the MIDI data rate. Refer to the Configuration Registers for information on disabling, power down and changing the base address of the UARTs. The interrupt from a UART is enabled by programming OUT2 of that UART to a logic "1". OUT2 being a logic "0" disables that UART's interrupt. The second UART also supports IrDA 1.2 (4Mbps), HP-SIR, ASK-IR and Consumer IR infrared modes of operation. 8.8.1 Register Description Addressing of the accessible registers of the Serial Port is shown below. The base addresses of the serial ports are defined by the configuration registers (see Configuration section). The Serial Port registers are located at sequentially increasing addresses above these base addresses. The SIO10N268 contains two serial ports, each of which contain a register set as described below. Table 8.33 - Addressing the Serial Port DLAB* 0 0 0 X X X X X X X 1 1 A2 0 0 0 0 0 0 1 1 1 1 0 0 A1 0 0 0 1 1 1 0 0 1 1 0 0 A0 0 0 1 0 0 1 0 1 0 1 0 1 REGISTER NAME Receive Buffer (read) Transmit Buffer (write) Interrupt Enable (read/write) Interrupt Identification (read) FIFO Control (write) Line Control (read/write) Modem Control (read/write) Line Status (read/write) Modem Status (read/write) Scratchpad (read/write) Divisor LSB (read/write) Divisor MSB (read/write Page 91 Rev. 0.5 (03-24-05) SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet Note 8.14 DLAB is Bit 7 of the Line Control Register The following section describes the operation of the registers. 8.8.1.1 Receive Buffer Register (RB) Address Offset = 0H, DLAB = 0, READ ONLY This register holds the received incoming data byte. Bit 0 is the least significant bit, which is transmitted and received first. Received data is double buffered; this uses an additional shift register to receive the serial data stream and convert it to a parallel 8 bit word which is transferred to the Receive Buffer register. The shift register is not accessible. 8.8.1.2 Transmit Buffer Register (TB) Address Offset = 0H, DLAB = 0, WRITE ONLY This register contains the data byte to be transmitted. The transmit buffer is double buffered, utilizing an additional shift register (not accessible) to convert the 8 bit data word to a serial format. This shift register is loaded from the Transmit Buffer when the transmission of the previous byte is complete. 8.8.1.3 Interrupt Enable Register (IER) Address Offset = 1H, DLAB = 0, READ/WRITE The lower four bits of this register control the enables of the five interrupt sources of the Serial Port interrupt. It is possible to totally disable the interrupt system by resetting bits 0 through 3 of this register. Similarly, setting the appropriate bits of this register to a high, selected interrupts can be enabled. Disabling the interrupt system inhibits the Interrupt Identification Register and disables any Serial Port interrupt out of the SIO10N268. All other system functions operate in their normal manner, including the Line Status and MODEM Status Registers. The contents of the Interrupt Enable Register are described below. Bit 0 This bit enables the Received Data Available Interrupt (and timeout interrupts in the FIFO mode) when set to logic "1". Bit 1 This bit enables the Transmitter Holding Register Empty Interrupt when set to logic "1". Bit 2 This bit enables the Received Line Status Interrupt when set to logic "1". The error sources causing the interrupt are Overrun, Parity, Framing and Break. The Line Status Register must be read to determine the source. Bit 3 This bit enables the MODEM Status Interrupt when set to logic "1". This is caused when one of the Modem Status Register bits changes state. Rev. 0.5 (03-24-05) Page 92 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet Bits 4 through 7 These bits are always logic "0". 8.8.1.4 FIFO Control Register (FCR) Address Offset = 2H, DLAB = X, WRITE This is a write only register at the same location as the IIR. This register is used to enable and clear the FIFOs, set the RCVR FIFO trigger level. Note: DMA is not supported. The UART1 and UART2 FCR's are shadowed in the UART1 FIFO Control Shadow Register (CR15) and UART2 FIFO Control Shadow Register (CR16). See the Configuration section for description on these registers. Bit 0 Setting this bit to a logic "1" enables both the XMIT and RCVR FIFOs. Clearing this bit to a logic "0" disables both the XMIT and RCVR FIFOs and clears all bytes from both FIFOs. When changing from FIFO Mode to non-FIFO (16450) mode, data is automatically cleared from the FIFOs. This bit must be a 1 when other bits in this register are written to or they will not be properly programmed. Bit 1 Setting this bit to a logic "1" clears all bytes in the RCVR FIFO and resets its counter logic to 0. The shift register is not cleared. This bit is self-clearing. Bit 2 Setting this bit to a logic "1" clears all bytes in the XMIT FIFO and resets its counter logic to 0. The shift register is not cleared. This bit is self-clearing. Bit 3 Writing to this bit has no effect on the operation of the UART. DMA modes are not supported in this chip. Bit 4,5 Reserved Bit 6,7 These bits are used to set the trigger level for the RCVR FIFO interrupt. RCVR FIFO Trigger Level (BYTES) 1 4 8 14 Bit 7 0 0 1 1 Bit 6 0 1 0 1 SMSC SIO10N268 Page 93 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet 8.8.1.5 Interrupt Identification Register (IIR) Address Offset = 2H, DLAB = X, READ By accessing this register, the host CPU can determine the highest priority interrupt and its source. Four levels of priority interrupt exist. They are in descending order of priority: 1) 2) 3) 4) Receiver Line Status (highest priority) Received Data Ready Transmitter Holding Register Empty MODEM Status (lowest priority) Information indicating that a prioritized interrupt is pending and the source of that interrupt is stored in the Interrupt Identification Register (refer to Interrupt Control Table). When the CPU accesses the IIR, the Serial Port freezes all interrupts and indicates the highest priority pending interrupt to the CPU. During this CPU access, even if the Serial Port records new interrupts, the current indication does not change until access is completed. The contents of the IIR are described below. Bit 0 This bit can be used in either a hardwired prioritized or polled environment to indicate whether an interrupt is pending. When bit 0 is a logic "0", an interrupt is pending and the contents of the IIR may be used as a pointer to the appropriate internal service routine. When bit 0 is a logic "1", no interrupt is pending. Bits 1 and 2 These two bits of the IIR are used to identify the highest priority interrupt pending as indicated by the Interrupt Control Table. Bit 3 In non-FIFO mode, this bit is a logic "0". In FIFO mode this bit is set along with bit 2 when a timeout interrupt is pending. Bits 4 and 5 These bits of the IIR are always logic "0". Bits 6 and 7 These two bits are set when the FIFO CONTROL Register bit 0 equals 1. Rev. 0.5 (03-24-05) Page 94 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet Table 8.34 - Interrupt Control Table FIFO MODE ONLY BIT 3 0 0 INTERRUPT IDENTIFICATION REGISTER BIT 2 0 1 BIT 1 0 1 PRIORITY BIT 0 LEVEL 1 0 Highest INTERRUPT SET AND RESET FUNCTIONS INTERRUPT TYPE None Receiver Line Status INTERRUPT SOURCE None Overrun Error, Parity Error, Framing Error or Break Interrupt Receiver Data Available INTERRUPT RESET CONTROL Reading the Line Status Register 0 1 0 0 Second Received Data Available 1 1 0 0 Second 0 0 1 0 Third 0 0 0 0 Fourth No Characters Have Been Removed From or Input to the RCVR FIFO during the last 4 Char times and there is at least 1 char in it during this time Reading the IIR Transmitter Transmitter Register (if Source Holding Register Holding of Interrupt) or Register Empty Empty Writing the Transmitter Holding Register Reading the MODEM Status Clear to Send or Data Set Ready or MODEM Status Register Ring Indicator or Data Carrier Detect Character Timeout Indication Read Receiver Buffer or the FIFO drops below the trigger level. Reading the Receiver Buffer Register 8.8.1.6 Line Control Register (LCR) Address Offset = 3H, DLAB = 0, READ/WRITE Start LSB Data 5-8 bits MSB Parity Stop Figure 8.7 - Serial Data This register contains the format information of the serial line. The bit definitions are: Bits 0 and 1 These two bits specify the number of bits in each transmitted or received serial character. The encoding of bits 0 and 1 is as follows: SMSC SIO10N268 Page 95 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet The Start, Stop and Parity bits are not included in the word length. BIT 1 0 0 1 1 Bit 2 This bit specifies the number of stop bits in each transmitted or received serial character. The following table summarizes the information. NUMBER OF STOP BITS 1 1.5 2 2 2 BIT 0 0 1 0 1 WORD LENGTH 5 Bits 6 Bits 7 Bits 8 Bits BIT 2 0 1 1 1 1 NOTE: WORD LENGTH -5 bits 6 bits 7 bits 8 bits The receiver will ignore all stop bits beyond the first, regardless of the number used in transmitting. Bit 3 Parity Enable bit. When bit 3 is a logic "1", a parity bit is generated (transmit data) or checked (receive data) between the last data word bit and the first stop bit of the serial data. (The parity bit is used to generate an even or odd number of 1s when the data word bits and the parity bit are summed). Bit 4 Even Parity Select bit. When bit 3 is a logic "1" and bit 4 is a logic "0", an odd number of logic "1"'s is transmitted or checked in the data word bits and the parity bit. When bit 3 is a logic "1" and bit 4 is a logic "1" an even number of bits is transmitted and checked. Bit 5 Stick Parity bit. When parity is enabled it is used in conjunction with bit 4 to select Mark or Space Parity. When LCR bits 3, 4 and 5 are 1 the Parity bit is transmitted and checked as 0 (Space Parity). If bits 3 and 5 are 1 and bit 4 is a 0, then the Parity bit is transmitted and checked as 1 (Mark Parity). If bit 5 is 0 Stick Parity is disabled. Bit 6 Set Break Control bit. When bit 6 is a logic "1", the transmit data output (TXD) is forced to the Spacing or logic "0" state and remains there (until reset by a low level bit 6) regardless of other transmitter activity. This feature enables the Serial Port to alert a terminal in a communications system. Bit 7 Divisor Latch Access bit (DLAB). It must be set high (logic "1") to access the Divisor Latches of the Baud Rate Generator during read or write operations. It must be set low (logic "0") to access the Receiver Buffer Register, the Transmitter Holding Register, or the Interrupt Enable Register. Rev. 0.5 (03-24-05) Page 96 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet 8.8.1.7 Modem Control Register (MCR) Address Offset = 4H, DLAB = X, READ/WRITE This 8 bit register controls the interface with the MODEM or data set (or device emulating a MODEM). The contents of the MODEM control register are described below. Bit 0 This bit controls the Data Terminal Ready (nDTR) output. When bit 0 is set to a logic "1", the nDTR output is forced to a logic "0". When bit 0 is a logic "0", the nDTR output is forced to a logic "1". Bit 1 This bit controls the Request To Send (nRTS) output. Bit 1 affects the nRTS output in a manner identical to that described above for bit 0. Bit 2 This bit controls the Output 1 (OUT1) bit. This bit does not have an output pin and can only be read or written by the CPU. Bit 3 Output 2 (OUT2). This bit is used to enable an UART interrupt. When OUT2 is a logic "0", the serial port interrupt output is forced to a high impedance state - disabled. When OUT2 is a logic "1", the serial port interrupt outputs are enabled. Bit 4 This bit provides the loopback feature for diagnostic testing of the Serial Port. When bit 4 is set to logic "1", the following occur: 1) 2) 3) 4) 5) The TXD is set to the Marking State(logic "1"). The receiver Serial Input (RXD) is disconnected. The output of the Transmitter Shift Register is "looped back" into the Receiver Shift Register input. All MODEM Control inputs (nCTS, nDSR, nRI and nDCD) are disconnected. The four MODEM Control outputs (nDTR, nRTS, OUT1 and OUT2) are internally connected to the four MODEM Control inputs (nDSR, nCTS, RI, DCD). The Modem Control output pins are forced inactive high. Data that is transmitted is immediately received. In the Control Control Enable 6) 7) This feature allows the processor to verify the transmit and receive data paths of the Serial Port. diagnostic mode, the receiver and the transmitter interrupts are fully operational. The MODEM Interrupts are also operational but the interrupts' sources are now the lower four bits of the MODEM Register instead of the MODEM Control inputs. The interrupts are still controlled by the Interrupt Register. Bits 5 through 7 SMSC SIO10N268 Page 97 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet These bits are permanently set to logic zero. 8.8.1.8 Line Status Register (LSR) Address Offset = 5H, DLAB = X, READ/WRITE Bit 0 Data Ready (DR). It is set to a logic "1" whenever a complete incoming character has been received and transferred into the Receiver Buffer Register or the FIFO. Bit 0 is reset to a logic "0" by reading all of the data in the Receive Buffer Register or the FIFO. Bit 1 Overrun Error (OE). Bit 1 indicates that data in the Receiver Buffer Register was not read before the next character was transferred into the register, thereby destroying the previous character. In FIFO mode, an overrunn error will occur only when the FIFO is full and the next character has been completely received in the shift register, the character in the shift register is overwritten but not transferred to the FIFO. The OE indicator is set to a logic "1" immediately upon detection of an overrun condition, and reset whenever the Line Status Register is read. Bit 2 Parity Error (PE). Bit 2 indicates that the received data character does not have the correct even or odd parity, as selected by the even parity select bit. The PE is set to a logic "1" upon detection of a parity error and is reset to a logic "0" whenever the Line Status Register is read. In the FIFO mode this error is associated with the particular character in the FIFO it applies to. This error is indicated when the associated character is at the top of the FIFO. Bit 3 Framing Error (FE). Bit 3 indicates that the received character did not have a valid stop bit. Bit 3 is set to a logic "1" whenever the stop bit following the last data bit or parity bit is detected as a zero bit (Spacing level). The FE is reset to a logic "0" whenever the Line Status Register is read. In the FIFO mode this error is associated with the particular character in the FIFO it applies to. This error is indicated when the associated character is at the top of the FIFO. The Serial Port will try to resynchronize after a framing error. To do this, it assumes that the framing error was due to the next start bit, so it samples this 'start' bit twice and then takes in the 'data'. Bit 4 Break Interrupt (BI). Bit 4 is set to a logic "1" whenever the received data input is held in the Spacing state (logic "0") for longer than a full word transmission time (that is, the total time of the start bit + data bits + parity bits + stop bits). The BI is reset after the CPU reads the contents of the Line Status Register. In the FIFO mode this error is associated with the particular character in the FIFO it applies to. This error is indicated when the associated character is at the top of the FIFO. When break occurs only one zero character is loaded into the FIFO. Restarting after a break is received, requires the serial data (RXD) to be logic "1" for at least 1/2 bit time. NOTE: Bits 1 through 4 are the error conditions that produce a Receiver Line Status Interrupt whenever any of the corresponding conditions are detected and the interrupt is enabled. Bit 5 Transmitter Holding Register Empty (THRE). Bit 5 indicates that the Serial Port is ready to accept a new character for transmission. In addition, this bit causes the Serial Port to issue an interrupt when the Transmitter Holding Register interrupt enable is set high. The THRE bit is set to a logic "1" when a character Rev. 0.5 (03-24-05) Page 98 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet is transferred from the Transmitter Holding Register into the Transmitter Shift Register. The bit is reset to logic "0" whenever the CPU loads the Transmitter Holding Register. In the FIFO mode this bit is set when the XMIT FIFO is empty, it is cleared when at least 1 byte is written to the XMIT FIFO. Bit 5 is a read only bit. Bit 6 Transmitter Empty (TEMT). Bit 6 is set to a logic "1" whenever the Transmitter Holding Register (THR) and Transmitter Shift Register (TSR) are both empty. It is reset to logic "0" whenever either the THR or TSR contains a data character. Bit 6 is a read only bit. In the FIFO mode this bit is set whenever the THR and TSR are both empty. Bit 7 This bit is permanently set to logic "0" in the 450 mode. In the FIFO mode, this bit is set to a logic "1" when there is at least one parity error, framing error or break indication in the FIFO. This bit is cleared when the LSR is read if there are no subsequent errors in the FIFO. 8.8.1.9 Modem Status Register (MSR) Address Offset = 6H, DLAB = X, READ/WRITE This 8 bit register provides the current state of the control lines from the MODEM (or peripheral device). In addition to this current state information, four bits of the MODEM Status Register (MSR) provide change information. These bits are set to logic "1" whenever a control input from the MODEM changes state. They are reset to logic "0" whenever the MODEM Status Register is read. Bit 0 Delta Clear To Send (DCTS). Bit 0 indicates that the nCTS input to the chip has changed state since the last time the MSR was read. Bit 1 Delta Data Set Ready (DDSR). Bit 1 indicates that the nDSR input has changed state since the last time the MSR was read. Bit 2 Trailing Edge of Ring Indicator (TERI). Bit 2 indicates that the nRI input has changed from logic "0" to logic "1". Bit 3 Delta Data Carrier Detect (DDCD). Bit 3 indicates that the nDCD input to the chip has changed state. NOTE: Whenever bit 0, 1, 2, or 3 is set to a logic "1", a MODEM Status Interrupt is generated. Bit 4 This bit is the complement of the Clear To Send (nCTS) input. If bit 4 of the MCR is set to logic "1", this bit is equivalent to nRTS in the MCR. Bit 5 This bit is the complement of the Data Set Ready (nDSR) input. If bit 4 of the MCR is set to logic "1", this bit is equivalent to DTR in the MCR. SMSC SIO10N268 Page 99 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet Bit 6 This bit is the complement of the Ring Indicator (nRI) input. If bit 4 of the MCR is set to logic "1", this bit is equivalent to OUT1 in the MCR. Bit 7 This bit is the complement of the Data Carrier Detect (nDCD) input. If bit 4 of the MCR is set to logic "1", this bit is equivalent to OUT2 in the MCR. 8.8.1.10 Scratchpad Register (SCR) Address Offset =7H, DLAB =X, READ/WRITE This 8 bit read/write register has no effect on the operation of the Serial Port. scratchpad register to be used by the programmer to hold data temporarily. It is intended as a 8.8.2 Programmable Baud Rate Generator (AND Divisor Latches DLH, DLL) The Serial Ports contains a programmable Baud Rate Generator that is capable of dividing the internal PLL clock by any divisor from 1 to 65535. The internal PLL clock is divided down to generate a 1.8462MHz frequency for Baud Rates less than 38.4k, a 1.8432MHz frequency for 115.2k, a 3.6864MHz frequency for 230.4k and a 7.3728MHz frequency for 460.8k. This output frequency of the Baud Rate Generator is 16x the Baud rate. Two 8 bit latches store the divisor in 16 bit binary format. These Divisor Latches must be loaded during initialization in order to insure desired operation of the Baud Rate Generator. Upon loading either of the Divisor Latches, a 16 bit Baud counter is immediately loaded. This prevents long counts on initial load. If a 0 is loaded into the BRG registers the output divides the clock by the number 3. If a 1 is loaded the output is the inverse of the input oscillator. If a two is loaded the output is a divide by 2 signal with a 50% duty cycle. If a 3 or greater is loaded the output is low for 2 bits and high for the remainder of the count. The input clock to the BRG is a 1.8462 MHz clock. Table 8.35 shows the baud rates possible. 8.8.3 Effect Of The Reset on Register File The Reset Function Table (Table 8.36) details the effect of the Reset input on each of the registers of the Serial Port. 8.8.4 FIFO Interrupt Mode Operation When the RCVR FIFO and receiver interrupts are enabled (FCR bit 0 = "1", IER bit 0 = "1"), RCVR interrupts occur as follows: a) The receive data available interrupt will be issued when the FIFO has reached its programmed trigger level; it is cleared as soon as the FIFO drops below its programmed trigger level. b) The IIR receive data available indication also occurs when the FIFO trigger level is reached. It is cleared when the FIFO drops below the trigger level. c) The receiver line status interrupt (IIR=06H), has higher priority than the received data available (IIR=04H) interrupt. Rev. 0.5 (03-24-05) Page 100 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet d) The data ready bit (LSR bit 0) is set as soon as a character is transferred from the shift register to the RCVR FIFO. It is reset when the FIFO is empty. When RCVR FIFO and receiver interrupts are enabled, RCVR FIFO timeout interrupts occur as follows: a) A FIFO timeout interrupt occurs if all the following conditions exist: At least one character is in the FIFO. The most recent serial character received was longer than 4 continuous character times ago. (If 2 stop bits are programmed, the second one is included in this time delay). The most recent CPU read of the FIFO was longer than 4 continuous character times ago. This will cause a maximum character received to interrupt issued delay of 160 msec at 300 BAUD with a 12 bit character. b) Character times are calculated by using the RCLK input for a clock signal (this makes the delay proportional to the baudrate). c) When a timeout interrupt has occurred it is cleared and the timer reset when the CPU reads one character from the RCVR FIFO. d) When a timeout interrupt has not occurred the timeout timer is reset after a new character is received or after the CPU reads the RCVR FIFO. When the XMIT FIFO and transmitter interrupts are enabled (FCR bit 0 = "1", IER bit 1 = "1"), XMIT interrupts occur as follows: a) The transmitter holding register interrupt (02H) occurs when the XMIT FIFO is empty; it is cleared as soon as the transmitter holding register is written to (1 of 16 characters may be written to the XMIT FIFO while servicing this interrupt) or the IIR is read. The transmitter FIFO empty indications will be delayed 1 character time minus the last stop bit time whenever the following occurs: THRE=1 and there have not been at least two bytes at the same time in the transmitter FIFO since the last THRE=1. The transmitter interrupt after changing FCR0 will be immediate, if it is enabled. b) Character timeout and RCVR FIFO trigger level interrupts have the same priority as the current received data available interrupt; XMIT FIFO empty has the same priority as the current transmitter holding register empty interrupt. 8.8.5 FIFO Polled Mode Operation With FCR bit 0 = "1" resetting IER bits 0, 1, 2 or 3 or all to zero puts the UART in the FIFO Polled mode of operation. Since the RCVR and XMITTER are controlled separately, either one or both can be in the polled mode of operation. In this mode, the user's program will check RCVR and XMITTER status via the LSR. LSR definitions for the FIFO Polled Mode are as follows: Bit 0=1 as long as there is one byte in the RCVR FIFO. Bits 1 to 4 specify which error(s) have occurred. Character error status is handled the same way as when in the interrupt mode, the IIR is not affected since EIR bit 2=0. Bit 5 indicates when the XMIT FIFO is empty. Bit 6 indicates that both the XMIT FIFO and shift register are empty. Bit 7 indicates whether there are any errors in the RCVR FIFO. SMSC SIO10N268 Page 101 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet There is no trigger level reached or timeout condition indicated in the FIFO Polled Mode, however, the RCVR and XMIT FIFOs are still fully capable of holding characters. Table 8.35 - Baud Rates DESIRED BAUD RATE 50 75 110 134.5 150 300 600 1200 1800 2000 2400 3600 4800 7200 9600 19200 38400 57600 115200 230400 460800 Note 8.15 Note 8.16 DIVISOR USED TO GENERATE 16X CLOCK 2304 1536 1047 857 768 384 192 96 64 58 48 32 24 16 12 6 3 2 1 32770 32769 PERCENT ERROR DIFFERENCE BETWEEN DESIRED AND ACTUAL (Note 8.15) 0.001 0.004 0.005 0.030 0.16 0.16 0.16 0.16 HIGH SPEED BIT (Note 8.16) X X X X X X X X X X X X X X X X X X X 1 1 The percentage error for all baud rates, except where indicated otherwise, is 0.2%. The High Speed bit is located in the Device Configuration Space. Table 8.36 - Reset Function Table REGISTER/SIGNAL Interrupt Enable Register Interrupt Identification Reg. FIFO Control Line Control Reg. MODEM Control Reg. Line Status Reg. MODEM Status Reg. TXD1, TXD2 INTRPT (RCVR errs) INTRPT (RCVR Data Ready) INTRPT (THRE) OUT2B RTSB DTRB RESET CONTROL RESET RESET RESET RESET RESET RESET RESET RESET RESET/Read LSR RESET/Read RBR RESET/ReadIIR/Write THR RESET RESET RESET Page 102 RESET STATE All bits low Bit 0 is high; Bits 1 - 7 low All bits low All bits low All bits low All bits low except 5, 6 high Bits 0 - 3 low; Bits 4 - 7 input High Low Low Low High High High SMSC SIO10N268 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet REGISTER/SIGNAL OUT1B RCVR FIFO XMIT FIFO RESET CONTROL RESET RESET/ FCR1*FCR0/_FCR0 RESET/ FCR1*FCR0/_FCR0 RESET STATE High All Bits Low All Bits Low SMSC SIO10N268 Page 103 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet Table 8.37 - Register Summary for an Individual UART Channel REGISTER ADDRESS (Note 8.17) ADDR = 0 DLAB = 0 ADDR = 0 DLAB = 0 ADDR = 1 DLAB = 0 REGISTER NAME Receive Buffer Register (Read Only) Transmitter Holding Register (Write Only) Interrupt Enable Register REGISTER SYMBOL RBR THR IER BIT 0 BIT 1 BIT 2 Data Bit 2 Data Bit 2 Enable Receiver Line Status Interrupt (ELSI) Interrupt ID Bit BIT 3 Data Bit 3 Data Bit 3 Enable MODEM Status Interrupt (EMSI) BIT 4 Data Bit 4 Data Bit 4 0 BIT 5 Data Bit 5 Data Bit 5 0 BIT 6 Data Bit 6 Data Bit 6 0 BIT 7 Data Bit 7 Data Bit 7 0 Data Bit 0 Data Bit 1 (Note 8.18) Data Bit 0 Enable Received Data Available Interrupt (ERDAI) "0" if Interrupt Pending FIFO Enable Data Bit 1 Enable Transmitter Holding Register Empty Interrupt (ETHREI) Interrupt ID Bit ADDR = 2 Interrupt Ident. Register (Read Only) IIR ADDR = 2 FIFO Control Register (Write Only) FCR (Note 8.24) RCVR FIFO Reset ADDR = 3 Line Control Register LCR Word Length Select Bit 0 (WLS0) Data Terminal Ready (DTR) Data Ready (DR) Word Length Select Bit 1 (WLS1) Interrupt ID Bit (Note 8.22) XMIT DMA FIFO Mode Reset Select (Note 8.23) Number Parity of Stop Enable Bits (STB) (PEN) 0 0 FIFOs Enabled (Note 8.22) RCVR Trigger LSB FIFOs Enabled (Note 8.22) RCVR Trigger MSB Reserve d Reserved Even Parity Select (EPS) Loop Stick Parity Set Break Divisor Latch Access Bit (DLAB) 0 ADDR = 4 MODEM Control Register MCR Request to OUT1 Send (RTS) (Note 8.20) Overrun Error (OE) OUT2 (Note 8.20) 0 0 ADDR = 5 Line Status Register LSR Parity Framing Error (PE) Error (FE) Trailing Edge Ring Indicator (TERI) Delta Data Carrier Detect (DDCD) Break Interrupt (BI) Clear to Send (CTS) ADDR = 6 MODEM Status Register MSR Delta Clear Delta Data to Send Set Ready (DCTS) (DDSR) Transmitter Holding Register (THRE) Data Set Ready (DSR) Transmitter Empty (TEMT) (Note 8.19) Ring Indicator (RI) Error in RCVR FIFO (Note 8.22) Data Carrier Detect (DCD) Rev. 0.5 (03-24-05) Page 106 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet REGISTER ADDRESS (Note 8.17) ADDR = 7 ADDR = 0 DLAB = 1 ADDR = 1 DLAB = 1 REGISTER NAME Scratch Register (Note 8.21) Divisor Latch (LS) Divisor Latch (MS) REGISTER SYMBOL SCR DDL DLM BIT 0 Bit 0 Bit 0 Bit 8 BIT 1 Bit 1 Bit 1 Bit 9 BIT 2 Bit 2 Bit 2 Bit 10 BIT 3 Bit 3 Bit 3 Bit 11 BIT 4 Bit 4 Bit 4 Bit 12 BIT 5 Bit 5 Bit 5 Bit 13 BIT 6 Bit 6 Bit 6 Bit 14 BIT 7 Bit 7 Bit 7 Bit 15 Note 8.17 Note 8.18 Note 8.19 Note 8.20 Note 8.21 Note 8.22 Note 8.23 Note 8.24 DLAB is Bit 7 of the Line Control Register (ADDR = 3). Bit 0 is the least significant bit. It is the first bit serially transmitted or received. When operating in the XT mode, this bit will be set any time that the transmitter shift register is empty. This bit no longer has a pin associated with it. When operating in the XT mode, this register is not available. These bits are always zero in the non-FIFO mode. Writing a one to this bit has no effect. DMA modes are not supported in this chip. The UART1 and UART2 FCR's are shadowed in the UART1 FIFO Control Shadow Register (CR15) and UART2 FIFO Control Shadow Register (CR16). SMSC SIO10N268 Page 107 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet 8.8.6 8.8.6.1 Notes On Serial Port Operation FIFO Mode Operation General The RCVR FIFO will hold up to 16 bytes regardless of which trigger level is selected. 8.8.6.2 TX and RX FIFO Operation The Tx portion of the UART transmits data through TXD as soon as the CPU loads a byte into the Tx FIFO. The UART will prevent loads to the Tx FIFO if it currently holds 16 characters. Loading to the Tx FIFO will again be enabled as soon as the next character is transferred to the Tx shift register. These capabilities account for the largely autonomous operation of the Tx. The UART starts the above operations typically with a Tx interrupt. The chip issues a Tx interrupt whenever the Tx FIFO is empty and the Tx interrupt is enabled, except in the following instance. Assume that the Tx FIFO is empty and the CPU starts to load it. When the first byte enters the FIFO the Tx FIFO empty interrupt will transition from active to inactive. Depending on the execution speed of the service routine software, the UART may be able to transfer this byte from the FIFO to the shift register before the CPU loads another byte. If this happens, the Tx FIFO will be empty again and typically the UART's interrupt line would transition to the active state. This could cause a system with an interrupt control unit to record a Tx FIFO empty condition, even though the CPU is currently servicing that interrupt. Therefore, after the first byte has been loaded into the FIFO the UART will wait one serial character transmission time before issuing a new Tx FIFO empty interrupt. This one character Tx interrupt delay will remain active until at least two bytes have been loaded into the FIFO, concurrently. When the Tx FIFO empties after this condition, the Tx interrupt will be activated without a one character delay. Rx support functions and operation are quite different from those described for the transmitter. The Rx FIFO receives data until the number of bytes in the FIFO equals the selected interrupt trigger level. At that time if Rx interrupts are enabled, the UART will issue an interrupt to the CPU. The Rx FIFO will continue to store bytes until it holds 16 of them. It will not accept any more data when it is full. Any more data entering the Rx shift register will set the Overrun Error flag. Normally, the FIFO depth and the programmable trigger levels will give the CPU ample time to empty the Rx FIFO before an overrun occurs. One side-effect of having a Rx FIFO is that the selected interrupt trigger level may be above the data level in the FIFO. This could occur when data at the end of the block contains fewer bytes than the trigger level. No interrupt would be issued to the CPU and the data would remain in the UART. To prevent the software from having to check for this situation the chip incorporates a timeout interrupt. The timeout interrupt is activated when there is a least one byte in the Rx FIFO, and neither the CPU nor the Rx shift register has accessed the Rx FIFO within 4 character times of the last byte. The timeout interrupt is cleared or reset when the CPU reads the Rx FIFO or another character enters it. These FIFO related features allow optimization of CPU/UART transactions and are especially useful given the higher baud rate capability (256 kbaud). 8.9 Infrared Interface The SIO10N268 infrared interface provides a two-way wireless communications port using infrared as the transmission medium. Several infrared protocols have been provided in this implementation including IrDA Rev. 0.5 (03-24-05) Page 108 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet v1.2 (SIR/FIR), ASKIR, and Consumer IR (Figure 8.8). For more information, consult the SMSC Infrared Communication Controller (IRCC) specification. The IrDA v1.0 (SIR) and ASKIR formats are driven by the ACE registers found in UART2. The UART2 registers are described in "Serial Port (UART)" section. The base address for UART2 is programmed in CR25, the UART2 Base Address Register (see section CR25 subsection in the Configuration seciton). The IrDA V1.2 (FIR) and Consumer IR formats are driven by the SCE registers. Descriptions of these registers can be found in the SMSC Infrared Communications Controller Specification. The Base Address for the SCE registers is programmed in CR2B, the SCE Base Address Register (see CR28 subsection in the Configuration section). 8.9.1 IrDA SIR/FIR and ASKIR IrDA SIR (v1.0) specifies asynchronous serial communication at baud rates up to 115.2Kbps. Each byte is sent serially LSB first beginning with a zero value start bit. A zero is signaled by sending a single infrared pulse at the beginning of the serial bit time. A one is signaled by the absence of an infrared pulse during the bit time. Please refer to "Timing Diagrams" section for the parameters of these pulses and the IrDA waveforms. IrDA FIR (v1.2) includes IrDA v1.0 SIR and additionally specifies synchronous serial communications at data rates up to 4Mbps. Data is transferred LSB first in packets that can be up to 2048 bits in length. IrDA v1.2 includes .576Mbps and 1.152Mbps data rates using an encoding scheme that is similar to SIR. The 4Mbps data rate uses a pulse position modulation (PPM) technique. The ASKIR infrared allows asynchronous serial communication at baud rates up to 19.2Kbps. Each byte is sent serially LSB first beginning with a zero value start bit. A zero is signaled by sending a 500KHz carrier waveform for the duration of the serial bit time. A one is signaled by the absence of carrier during the bit time. Refer to "Timing Diagrams" section for the parameters of the ASKIR waveforms. 8.9.2 Consumer IR The SIO10N268 Consumer IR interface is a general-purpose Amplitude Shift Keyed encoder/decoder with programmable carrier and bit-cell rates that can emulate many popular TV Remote encoding formats; including, 38KHz PPM, PWM and RC-5. The carrier frequency is programmable from 1.6MHz to 6.25KHz. The bit-cell rate range is 100KHz to 390Hz. 8.9.3 Hardware Interface The SIO10N268 IR hardware interface is shown in Figure 8.8. This interface supports two types of external FIR transceiver modules. One uses a mode pin (IR Mode) to program the data rate, while the other has a second Rx data pin (IRRX3). The SIO10N268 uses Pin 63 for these functions. Pin 62 has IR Mode and IRRX3 as its first and second alternate function, respectively. These functions are selected through CR29 as shown in Table 8.38. SMSC SIO10N268 Page 109 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet Table 8.38 - FIR Transceiver Module-Type Select HP MODE (Note 8.25) 0 1 Note 8.25 FUNCTION IR Mode IRRX3 HPMODE is CR29, BIT 4 (see CR29 subsection in the Configuration section). Refer to the Infrared Interface Block Diagram on the following page for HPMODE implementation. The FAST bit is used to select between the SIR mode and FIR mode receiver, regardless of the transceiver type. If FAST = 1, the FIR mode receiver is selected; if FAST = 0, the SIR mode receiver is selected (Table 8.39). Table 8.39 - IR Rx Data Pin Selection CONTROL SIGNALS FAST 0 X 1 HPMODE X 0 1 RX1 RX1=RXD2 RX1=RXD2 RX1=IR Mode/IRRX3 INPUTS RX2 RX2=IRRX2 RX2=IRRX2 RX2=IR Mode/IRRX3 8.9.4 IR Half Duplex Turnaround Delay Time If the Half Duplex option is chosen there is an IR Half Duplex Time-out that constrains IRCC direction mode changes. This time-out starts as each bit is transferred and prevents direction mode changes until the time-out expires. The timer is restarted whenever new data arrives in the current direction mode. For example, if data is loaded into the transmit buffer while a character is being received, the transmission will not start until the last bit has been received and the time-out expires. If the start bit of another character is received during this time-out, the timer is restarted after the new character is received. The Half Duplex Time-out is programmable from 0 to 25.5ms in 100s increments (see section (See subsection CR2D in the Configuration section). IrCC Block TX1 COM TV ASK IrDA FIR AUX COM IR MODE IR Mode /IRRX3 0 RAW TXD2 RX1 1 RXD2 1 TX2 OUT MUX IR RX2 1 IRTX2 2 0 IRRX2 TX3 RX3 G.P. Data Fast Bit FAST HPMODE Figure 8.8 - Infrared Interface Block Diagram Rev. 0.5 (03-24-05) Page 110 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet 8.9.5 IR Transmit Pins The IR transmit signal may be brought out onto the GP53/TXD2/IRTX pin or the GP21/IRTX2/WDT pin. These pins, which are not powered by VTR, function as described below. The following defines the acceptable states for the GP53/TXD2/IRTX output pin following a VCC POR or Hard Reset. If VCC=0V the GP53/TXD2/IRTX pin will be tristate. If VCC>2.4V and TXD2/IRTX functions are selected the following states are possible. - If UART2 Power bit = 0 OR bits[7:6] IR Output Mux EQUAL `11' at offset CR0A the output will be tristate - If UART2 Power bit = 1 AND bits[7:6] IR Output Mux EQUAL `00' at offset CR0A AND the transmit buffer is empty the output will be set to the inactive state. - If UART2 Power bit = 1 AND bits[7:6] IR Output Mux EQUAL `00' at offset CR0A AND the transmit buffer has data and is ready to transmit the output will reflect the state of the data being transmitted. - If UART2 Power bit = 1 AND bits[7:6] IR Output Mux EQUAL `01' at offset CR0A the output will be low. If VCC>2.4V and GP53 function is selected the pin will reflect the current state of GP53. The following defines the acceptable states for the GP21/IRTX2/WDT output pin following a VCC POR or Hard Reset. If VCC=0V the GP21/IRTX2/WDT pin will be tristate. If VCC>2.4V and IRTX2 function is selected the following states are possible. - If bits[7:6] IR Output Mux EQUAL `11' at offset CR0A the output will be tristate - If UART2 Power bit = 0 AND bits[7:6] IR Output Mux NOT EQUAL `11' at offset CR0A the output will be low. - If UART2 Power bit = 1 AND bits[7:6] IR Output Mux EQUAL `01' at offset CR0A AND the transmit buffer is empty the output will be set to the inactive state. - If UART2 Power bit = 1 AND bits[7:6] IR Output Mux EQUAL `01' at offset CR0A AND the transmit buffer has data and is ready to transmit the output will reflect the state of the data being transmitted. - If UART2 Power bit=1 AND bits[7:6] IR Output Mux EQUAL `00' the output will be low. If VCC>2.4V and GP21 function is selected the pin will reflect the current state of GP21. If VCC>2.4 and WDT function is selected the pin will reflect the current state of the WDT. NOTE: The inactive state for GP53/TXD2/IRTX pin or GP21/IRTX2/WDT pin is determined by a combination of the mode selected and the function enabled on the pin. If the TXD2/IRTX or IRTX2 functions are enabled the inactive state is determined by the IR Output Mux bits located in CR0A ECP FIFO Threshold/IR MUX register and the UART Mode register located at CR0C. 8.10 Parallel Port The SIO10N268 incorporates an IBM XT/AT compatible parallel port. This supports the optional PS/2 type bi-directional parallel port (SPP), the Enhanced Parallel Port (EPP) and the Extended Capabilities Port (ECP) parallel port modes. Refer to the Configuration Registers for information on disabling, power down, changing the base address of the parallel port, and selecting the mode of operation. The SIO10N268 also provides a mode for support of the floppy disk controller on the parallel port. The parallel port also incorporates SMSC's ChiProtect circuitry, which prevents possible damage to the parallel port due to printer power-up. SMSC SIO10N268 Page 111 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet The functionality of the Parallel Port is achieved through the use of eight addressable ports, with their associated registers and control gating. The control and data port are read/write by the CPU, the status port is read/write in the EPP mode. The address map of the Parallel Port is shown below. DATA PORT STATUS PORT CONTROL PORT EPP ADDR PORT EPP DATA PORT 0 EPP DATA PORT 1 EPP DATA PORT 2 EPP DATA PORT 3 The bit map of these registers is: DATA PORT STATUS PORT CONTROL PORT EPP ADDR PORT EPP DATA PORT 0 EPP DATA PORT 1 EPP DATA PORT 2 EPP DATA PORT 3 Note 8.26 Note 8.27 D0 PD0 TMOUT D1 PD1 0 D2 PD2 0 nINIT PD2 PD2 PD2 PD2 PD2 D3 PD3 nERR SLC PD3 PD3 PD3 PD3 PD3 D4 PD4 SLCT IRQE PD4 PD4 PD4 PD4 PD4 D5 PD5 PE PCD PD5 PD5 PD5 PD5 PD5 D6 PD6 nACK 0 PD6 PD6 PD6 PD6 PD6 D7 PD7 nBUSY 0 PD7 PD7 PD7 PD7 PD7 Note Note 8.26 Note 8.26 Note 8.26 Note 8.27 Note 8.27 Note 8.27 Note 8.27 Note 8.27 BASE ADDRESS + 00H BASE ADDRESS + 01H BASE ADDRESS + 02H BASE ADDRESS + 03H BASE ADDRESS + 04H BASE ADDRESS + 05H BASE ADDRESS + 06H BASE ADDRESS + 07H STROBE AUTOFD PD0 PD0 PD0 PD0 PD0 PD1 PD1 PD1 PD1 PD1 These registers are available in all modes. These registers are only available in EPP mode. Table 8.40 - Parallel Port Connector HOST CONNECTOR 1 2-9 10 11 12 13 14 15 PIN NUMBER 81 65-69, 71-73 78 77 76 75 80 79 STANDARD nSTROBE PD<0:7> nACK BUSY PE SLCT nALF nERROR EPP nWrite PData<0:7> Intr nWait (User Defined) (User Defined) nDatastb (User Defined) ECP nStrobe PData<0:7> nAck Busy, PeriphAck(3) PError, nAckReverse(3) Select nAutoFd, HostAck(3) nFault(1) nPeriphRequest(3) Rev. 0.5 (03-24-05) Page 112 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet HOST CONNECTOR 16 17 PIN NUMBER 63 64 STANDARD nINIT nSLCTIN EPP nRESET nAddrstrb ECP nInit(1) nReverseRqst(3) nSelectIn(1,3) (1) = Compatible Mode (3) = High Speed Mode NOTE: For the cable interconnection required for ECP support and the Slave Connector pin numbers, refer to the IEEE 1284 Extended Capabilities Port Protocol and ISA Standard, Rev. 1.14, July 14, 1993. This document is available from Microsoft. 8.10.1 IBM XT/AT Compatible, Bi-Directional And EPP Modes 8.10.1.1 Data Port ADDRESS OFFSET = 00H The Data Port is located at an offset of '00H' from the base address. The data register is cleared at initialization by RESET. During a WRITE operation, the Data Register latches the contents of the internal data bus. The contents of this register are buffered (non inverting) and output onto the PD0 - PD7 ports. During a READ operation in SPP mode, PD0 - PD7 ports are buffered (not latched) and output to the host CPU. 8.10.1.2 Status Port ADDRESS OFFSET = 01H The Status Port is located at an offset of '01H' from the base address. The contents of this register are latched for the duration of a read cycle. The bits of the Status Port are defined as follows: BIT 0 TMOUT - TIME OUT This bit is valid in EPP mode only and indicates that a 10 usec time out has occurred on the EPP bus. A logic zero means that no time out error has occurred; a logic 1 means that a time out error has been detected. The means of clearing the TIMEOUT bit is controlled by the TIMEOUT_SELECT bit as follows. The TIMEOUT_SELECT bit is located at bit 2 of CR21. If the TIMEOUT_SELECT bit is cleared (`0'), the TIMEOUT bit is cleared on the trailing edge of the read of the EPP Status Register (default) If the TIMEOUT_SELECT bit is set (`1'), the TIMEOUT bit is cleared on a write of `1' to the TIMEOUT bit. The TIMEOUT bit is cleared on PCI_RESET regardless of the state of the TIMEOUT_SELECT bit. BITS 1, 2 - are not implemented as register bits, during a read of the Printer Status Register these bits are a low level. BIT 3 nERR - nERROR SMSC SIO10N268 Page 113 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet The level on the nERROR input is read by the CPU as bit 3 of the Printer Status Register. A logic 0 means an error has been detected; a logic 1 means no error has been detected. BIT 4 SLCT - PRINTER SELECTED STATUS The level on the SLCT input is read by the CPU as bit 4 of the Printer Status Register. A logic 1 means the printer is on line; a logic 0 means it is not selected. BIT 5 PE - PAPER END The level on the PE input is read by the CPU as bit 5 of the Printer Status Register. A logic 1 indicates a paper end; a logic 0 indicates the presence of paper. BIT 6 nACK - nACKNOWLEDGE The level on the nACK input is read by the CPU as bit 6 of the Printer Status Register. A logic 0 means that the printer has received a character and can now accept another. A logic 1 means that it is still processing the last character or has not received the data. BIT 7 nBUSY - nBUSY The complement of the level on the BUSY input is read by the CPU as bit 7 of the Printer Status Register. A logic 0 in this bit means that the printer is busy and cannot accept a new character. A logic 1 means that it is ready to accept the next character. 8.10.1.3 Control Port ADDRESS OFFSET = 02H The Control Port is located at an offset of '02H' from the base address. The Control Register is initialized by the RESET input, bits 0 to 5 only being affected; bits 6 and 7 are hard wired low. BIT 0 STROBE - STROBE This bit is inverted and output onto the nSTROBE output. BIT 1 AUTOFD - AUTOFEED This bit is inverted and output onto the nAUTOFD output. A logic 1 causes the printer to generate a line feed after each line is printed. A logic 0 means no autofeed. BIT 2 nINIT - nINITIATE OUTPUT This bit is output onto the nINIT output without inversion. BIT 3 SLCTIN - PRINTER SELECT INPUT This bit is inverted and output onto the nSLCTIN output. A logic 1 on this bit selects the printer; a logic 0 means the printer is not selected. BIT 4 IRQE - INTERRUPT REQUEST ENABLE The interrupt request enable bit when set to a high level may be used to enable interrupt requests from the Parallel Port to the CPU. An interrupt request is generated on the IRQ port by a positive going nACK input. When the IRQE bit is programmed low the IRQ is disabled. Rev. 0.5 (03-24-05) Page 114 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet BIT 5 PCD - PARALLEL CONTROL DIRECTION Parallel Control Direction is not valid in printer mode. In printer mode, the direction is always out regardless of the state of this bit. In bi-directional, EPP or ECP mode, a logic 0 means that the printer port is in output mode (write); a logic 1 means that the printer port is in input mode (read). Bits 6 and 7 during a read are a low level, and cannot be written. 8.10.1.4 EPP Address Port ADDRESS OFFSET = 03H The EPP Address Port is located at an offset of '03H' from the base address. The address register is cleared at initialization by RESET. During a WRITE operation, the contents of the internal data bus DB0DB7 are buffered (non inverting) and output onto the PD0 - PD7 ports. An LPC I/O write cycle causes an EPP ADDRESS WRITE cycle to be performed, during which the data is latched for the duration of the EPP write cycle. During a READ operation, PD0 - PD7 ports are read. An LPC I/O read cycle causes an EPP ADDRESS READ cycle to be performed and the data output to the host CPU, the deassertion of ADDRSTB latches the PData for the duration of the read cycle. This register is only available in EPP mode. 8.10.1.5 EPP Data Port 0 ADDRESS OFFSET = 04H The EPP Data Port 0 is located at an offset of '04H' from the base address. The data register is cleared at initialization by RESET. During a WRITE operation, the contents of the internal data bus DB0-DB7 are buffered (non inverting) and output onto the PD0 - PD7 ports. An LPC I/O write cycle causes an EPP DATA WRITE cycle to be performed, during which the data is latched for the duration of the EPP write cycle. During a READ operation, PD0 - PD7 ports are read. An LPC I/O read cycle causes an EPP READ cycle to be performed and the data output to the host CPU, the deassertion of DATASTB latches the PData for the duration of the read cycle. This register is only available in EPP mode. 8.10.1.6 EPP Data Port 1 ADDRESS OFFSET = 05H The EPP Data Port 1 is located at an offset of '05H' from the base address. Refer to EPP DATA PORT 0 for a description of operation. This register is only available in EPP mode. 8.10.1.7 EPP Data Port 2 ADDRESS OFFSET = 06H The EPP Data Port 2 is located at an offset of '06H' from the base address. Refer to EPP DATA PORT 0 for a description of operation. This register is only available in EPP mode. 8.10.1.8 EPP Data Port 3 ADDRESS OFFSET = 07H The EPP Data Port 3 is located at an offset of '07H' from the base address. Refer to EPP DATA PORT 0 for a description of operation. This register is only available in EPP mode. SMSC SIO10N268 Page 115 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet 8.10.2 EPP 1.9 Operation When the EPP mode is selected in the configuration register, the standard and bi-directional modes are also available. If no EPP Read, Write or Address cycle is currently executing, then the PDx bus is in the standard or bi-directional mode, and all output signals (STROBE, AUTOFD, INIT) are as set by the SPP Control Port and direction is controlled by PCD of the Control port. In EPP mode, the system timing is closely coupled to the EPP timing. For this reason, a watchdog timer is required to prevent system lockup. The timer indicates if more than 10usec have elapsed from the start of the EPP cycle to nWAIT being deasserted (after command). If a time-out occurs, the current EPP cycle is aborted and the time-out condition is indicated in Status bit 0. During an EPP cycle, if STROBE is active, it overrides the EPP write signal forcing the PDx bus to always be in a write mode and the nWRITE signal to always be asserted. 8.10.2.1 Software Constraints Before an EPP cycle is executed, the software must ensure that the control register bit PCD is a logic "0" (i.e., a 04H or 05H should be written to the Control port). If the user leaves PCD as a logic "1", and attempts to perform an EPP write, the chip is unable to perform the write (because PCD is a logic "1") and will appear to perform an EPP read on the parallel bus, no error is indicated. 8.10.2.2 EPP 1.9 Write The timing for a write operation (address or data) is shown in timing diagram EPP Write Data or Address cycle. The chip inserts wait states into the LPC I/O write cycle until it has been determined that the write cycle can complete. The write cycle can complete under the following circumstances: 1) If the EPP bus is not ready (nWAIT is active low) when nDATASTB or nADDRSTB goes active then the write can complete when nWAIT goes inactive high. If the EPP bus is ready (nWAIT is inactive high) then the chip must wait for it to go active low before changing the state of nDATASTB, nWRITE or nADDRSTB. The write can complete once nWAIT is determined inactive. 2) Write Sequence of Operation 1) 2) 3) 4) The host initiates an I/O write cycle to the selected EPP register. If WAIT is not asserted, the chip must wait until WAIT is asserted. The chip places address or data on PData bus, clears PDIR, and asserts nWRITE. Chip asserts nDATASTB or nADDRSTRB indicating that PData bus contains valid information, and the WRITE signal is valid. Peripheral deasserts nWAIT, indicating that any setup requirements have been satisfied and the chip may begin the termination phase of the cycle. a) The chip deasserts nDATASTB or nADDRSTRB, this marks the beginning of the termination phase. If it has not already done so, the peripheral should latch the information byte now. b) The chip latches the data from the internal data bus for the PData bus and drives the sync that indicates that no more wait states are required followed by the TAR to complete the write cycle. 5) 6) Rev. 0.5 (03-24-05) Page 116 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet 7) Peripheral asserts nWAIT, indicating to the host that any hold time requirements have been satisfied and acknowledging the termination of the cycle. Chip may modify nWRITE and nPDATA in preparation for the next cycle. 8) 8.10.2.3 EPP 1.9 Read The timing for a read operation (data) is shown in timing diagram EPP Read Data cycle. The chip inserts wait states into the LPC I/O read cycle until it has been determined that the read cycle can complete. The read cycle can complete under the following circumstances: 1) If the EPP bus is not ready (nWAIT is active low) when nDATASTB goes active then the read can complete when nWAIT goes inactive high. If the EPP bus is ready (nWAIT is inactive high) then the chip must wait for it to go active low before changing the state of WRITE or before nDATASTB goes active. The read can complete once nWAIT is determined inactive. 2) Read Sequence of Operation 1) 2) 3) 4) The host initiates an I/O read cycle to the selected EPP register. If WAIT is not asserted, the chip must wait until WAIT is asserted. The chip tri-states the PData bus and deasserts nWRITE. Chip asserts nDATASTB or nADDRSTRB indicating that PData bus is tri-stated, PDIR is set and the nWRITE signal is valid. Peripheral drives PData bus valid. Peripheral deasserts nWAIT, indicating that PData is valid and the chip may begin the termination phase of the cycle. a) The chip latches the data from the PData bus for the internal data bus and deasserts nDATASTB or nADDRSTRB. This marks the beginning of the termination phase. b) The chip drives the sync that indicates that no more wait states are required and drives valid data onto the LAD[3:0] signals, followed by the TAR to complete the read cycle. 8) Peripheral tri-states the PData bus and asserts nWAIT, indicating to the host that the PData bus is tristated. Chip may modify nWRITE, PDIR and nPDATA in preparation for the next cycle. 5) 6) 7) 9) 8.10.3 EPP 1.7 Operation When the EPP 1.7 mode is selected in the configuration register, the standard and bi-directional modes are also available. If no EPP Read, Write or Address cycle is currently executing, then the PDx bus is in the standard or bi-directional mode, and all output signals (STROBE, AUTOFD, INIT) are as set by the SPP Control Port and direction is controlled by PCD of the Control port. In EPP mode, the system timing is closely coupled to the EPP timing. For this reason, a watchdog timer is required to prevent system lockup. The timer indicates if more than 10usec have elapsed from the start of SMSC SIO10N268 Page 117 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet the EPP cycle to the end of the cycle. If a time-out occurs, the current EPP cycle is aborted and the timeout condition is indicated in Status bit 0. 8.10.3.1 Software Constraints Before an EPP cycle is executed, the software must ensure that the control register bits D0, D1 and D3 are set to zero. Also, bit D5 (PCD) is a logic "0" for an EPP write or a logic "1" for and EPP read. 8.10.3.2 EPP 1.7 Write The timing for a write operation (address or data) is shown in timing diagram EPP 1.7 Write Data or Address cycle. The chip inserts wait states into the I/O write cycle when nWAIT is active low during the EPP cycle. This can be used to extend the cycle time. The write cycle can complete when nWAIT is inactive high. Write Sequence of Operation 1) 2) 3) 4) The host sets PDIR bit in the control register to a logic "0". This asserts nWRITE. The host initiates an I/O write cycle to the selected EPP register. The chip places address or data on PData bus. Chip asserts nDATASTB or nADDRSTRB indicating that PData bus contains valid information, and the WRITE signal is valid. If nWAIT is asserted, the chip inserts wait states into I/O write cycle until the peripheral deasserts nWAIT or a time-out occurs. The chip drives the final sync, deasserts nDATASTB or nADDRSTRB and latches the data from the internal data bus for the PData bus. Chip may modify nWRITE, PDIR and nPDATA in preparation of the next cycle. 5) 6) 7) 8.10.3.3 EPP 1.7 Read The timing for a read operation (data) is shown in timing diagram EPP 1.7 Read Data cycle. The chip inserts wait states into the I/O read cycle when nWAIT is active low during the EPP cycle. This can be used to extend the cycle time. The read cycle can complete when nWAIT is inactive high. Read Sequence of Operation 1) The host sets PDIR bit in the control register to a logic "1". This deasserts nWRITE and tri-states the PData bus. The host initiates an I/O read cycle to the selected EPP register. Chip asserts nDATASTB or nADDRSTRB indicating that PData bus is tri-stated, PDIR is set and the nWRITE signal is valid. If nWAIT is asserted, the chip inserts wait states into the I/O read cycle until the peripheral deasserts nWAIT or a time-out occurs. The Peripheral drives PData bus valid. 2) 3) 4) 5) Rev. 0.5 (03-24-05) Page 118 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet 6) The Peripheral deasserts nWAIT, indicating that PData is valid and the chip may begin the termination phase of the cycle. The chip drives the final sync and deasserts nDATASTB or nADDRSTRB. Peripheral tri-states the PData bus. Chip may modify nWRITE, PDIR and nPDATA in preparation of the next cycle. Table 8.41 - EPP Pin Descriptions 7) 8) 9) EPP SIGNAL nWRITE PD<0:7> INTR WAIT EPP NAME nWrite Address/Data Interrupt nWait TYPE O I/O I I DATASTB RESET ADDRSTB PE SLCT nERR Note 8.28 Note 8.29 nData Strobe nReset nAddress Strobe Paper End Printer Selected Status Error O O O I I I EPP DESCRIPTION This signal is active low. It denotes a write operation. Bi-directional EPP byte wide address and data bus. This signal is active high and positive edge triggered. (Pass through with no inversion, Same as SPP). This signal is active low. It is driven inactive as a positive acknowledgement from the device that the transfer of data is completed. It is driven active as an indication that the device is ready for the next transfer. This signal is active low. It is used to denote data read or write operation. This signal is active low. When driven active, the EPP device is reset to its initial operational mode. This signal is active low. It is used to denote address read or write operation. Same as SPP mode. Same as SPP mode. Same as SPP mode. SPP and EPP can use 1 common register. nWrite is the only EPP output that can be over-ridden by SPP control port during an EPP cycle. For correct EPP read cycles, PCD is required to be a low. 8.10.4 Extended Capabilities Parallel Port ECP provides a number of advantages, some of which are listed below. The individual features are explained in greater detail in the remainder of this section. High performance half-duplex forward and reverse channel Interlocked handshake, for fast reliable transfer Optional single byte RLE compression for improved throughput (64:1) Channel addressing for low-cost peripherals Maintains link and data layer separation Permits the use of active output drivers permits the use of adaptive signal timing Peer-to-peer capability. SMSC SIO10N268 Page 119 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet 8.10.5 Vocabulary The following terms are used in this document: assert: When a signal asserts it transitions to a "true" state, when a signal deasserts it transitions to a "false" state. forward: Host to Peripheral communication. reverse: Peripheral to Host communication Pword: A port word; equal in size to the width of the LPC interface. For this implementation, PWord is always 8 bits. 1 0 A high level. A low level. These terms may be considered synonymous: PeriphClk, nAck HostAck, nAutoFd PeriphAck, Busy nPeriphRequest, nFault nReverseRequest, nInit nAckReverse, PError Xflag, Select ECPMode, nSelectln HostClk, nStrobe Reference Document: IEEE 1284 Extended Capabilities Port Protocol and ISA Interface Standard, Rev 1.14, July 14, 1993. This document is available from Microsoft. The bit map of the Extended Parallel Port registers is: data ecpAFifo dsr dcr cFifo ecpDFifo tFifo cnfgA cnfgB ecr 0 0 compress intrValue MODE 0 D7 PD7 Addr/RLE nBusy 0 D6 PD6 D5 PD5 D4 D3 D2 PD4 PD3 PD2 Address or RLE field Select ackIntEn nFault SelectIn 0 nInit D1 PD1 D0 PD0 NOTE Note 8.31 Note 8.30 Note 8.30 Note 8.31 Note 8.31 Note 8.31 Note 8.32 nAck 0 PError Direction 0 autofd 0 strobe Parallel Port Data FIFO ECP Data FIFO Test FIFO 1 Parallel Port IRQ nErrIntrEn 0 0 0 0 Parallel Port DMA serviceIntr full empty dmaEn Rev. 0.5 (03-24-05) Page 120 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet Note 8.30 Note 8.31 Note 8.32 These registers are available in all modes. All FIFOs use one common 16 byte FIFO. The ECP Parallel Port Config Reg B reflects the IRQ and DMA channel selected by the Configuration Registers. 8.10.6 ECP Implementation Standard This specification describes the standard interface to the Extended Capabilities Port (ECP). All LPC devices supporting ECP must meet the requirements contained in this section or the port will not be supported by Microsoft. For a description of the ECP Protocol, please refer to the IEEE 1284 Extended Capabilities Port Protocol and ISA Interface Standard, Rev. 1.14, July 14, 1993. This document is available from Microsoft. 8.10.6.1 Description The port is software and hardware compatible with existing parallel ports so that it may be used as a standard LPT port if ECP is not required. The port is designed to be simple and requires a small number of gates to implement. It does not do any "protocol" negotiation, rather it provides an automatic high burst-bandwidth channel that supports DMA for ECP in both the forward and reverse directions. Small FIFOs are employed in both forward and reverse directions to smooth data flow and improve the maximum bandwidth requirement. The size of the FIFO is 16 bytes deep. The port supports an automatic handshake for the standard parallel port to improve compatibility mode transfer speed. The port also supports run length encoded (RLE) decompression (required) in hardware. Compression is accomplished by counting identical bytes and transmitting an RLE byte that indicates how many times the next byte is to be repeated. Decompression simply intercepts the RLE byte and repeats the following byte the specified number of times. Hardware support for compression is optional. Table 8.42 - ECP Pin Descriptions NAME nStrobe PData 7:0 nAck PeriphAck (Busy) TYPE O I/O I I DESCRIPTION During write operations nStrobe registers data or address into the slave on the asserting edge (handshakes with Busy). Contains address or data or RLE data. Indicates valid data driven by the peripheral when asserted. This signal handshakes with nAutoFd in reverse. This signal deasserts to indicate that the peripheral can accept data. This signal handshakes with nStrobe in the forward direction. In the reverse direction this signal indicates whether the data lines contain ECP command information or data. The peripheral uses this signal to flow control in the forward direction. It is an "interlocked" handshake with nStrobe. PeriphAck also provides command information in the reverse direction. Used to acknowledge a change in the direction the transfer (asserted = forward). The peripheral drives this signal low to acknowledge nReverseRequest. It is an "interlocked" handshake with nReverseRequest. The host relies upon nAckReverse to determine when it is permitted to drive the data bus. Indicates printer on line. PError (nAckReverse) I Select I SMSC SIO10N268 Page 121 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet NAME nAutoFd (HostAck) TYPE O nFault (nPeriphRequest) I nInit O nSelectIn O DESCRIPTION Requests a byte of data from the peripheral when asserted, handshaking with nAck in the reverse direction. In the forward direction this signal indicates whether the data lines contain ECP address or data. The host drives this signal to flow control in the reverse direction. It is an "interlocked" handshake with nAck. HostAck also provides command information in the forward phase. Generates an error interrupt when asserted. This signal provides a mechanism for peer-to-peer communication. This signal is valid only in the forward direction. During ECP Mode the peripheral is permitted (but not required) to drive this pin low to request a reverse transfer. The request is merely a "hint" to the host; the host has ultimate control over the transfer direction. This signal would be typically used to generate an interrupt to the host CPU. Sets the transfer direction (asserted = reverse, deasserted = forward). This pin is driven low to place the channel in the reverse direction. The peripheral is only allowed to drive the bi-directional data bus while in ECP Mode and HostAck is low and nSelectIn is high. Always deasserted in ECP mode. 8.10.6.2 Register Definitions The register definitions are based on the standard IBM addresses for LPT. All of the standard printer ports are supported. The additional registers attach to an upper bit decode of the standard LPT port definition to avoid conflict with standard ISA devices. The port is equivalent to a generic parallel port interface and may be operated in that mode. The port registers vary depending on the mode field in the ecr. The table below lists these dependencies. Operation of the devices in modes other that those specified is undefined. Table 8.43 - ECP Register Definitions NAME data ecpAFifo dsr dcr cFifo ecpDFifo tFifo cnfgA cnfgB ecr Note 8.33 ADDRESS (Note 8.33) +000h R/W +000h R/W +001h R/W +002h R/W +400h R/W +400h R/W +400h R/W +400h R +401h R/W +402h R/W ECP MODES 000-001 011 All All 010 011 110 111 111 All FUNCTION Data Register ECP FIFO (Address) Status Register Control Register Parallel Port Data FIFO ECP FIFO (DATA) Test FIFO Configuration Register A Configuration Register B Extended Control Register These addresses are added to the parallel port base address as selected by configuration register or jumpers. All addresses are qualified with AEN. Refer to the AEN pin definition. Table 8.44 - Mode Descriptions MODE 000 001 010 011 DESCRIPTION (Note 8.35) SPP mode PS/2 Parallel Port mode Parallel Port Data FIFO mode ECP Parallel Port mode Note 8.34 Rev. 0.5 (03-24-05) Page 122 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet MODE 100 101 110 111 Note 8.35 DESCRIPTION (Note 8.35) EPP mode (If this option is enabled in the configuration registers) Reserved Test mode Configuration mode Refer to ECR Register Description Data And ecpAFifo Port ADDRESS OFFSET = 00H Modes 000 and 001 (Data Port) The Data Port is located at an offset of '00H' from the base address. The data register is cleared at initialization by RESET. During a WRITE operation, the Data Register latches the contents of the data bus. The contents of this register are buffered (non inverting) and output onto the PD0 - PD7 ports. During a READ operation, PD0 - PD7 ports are read and output to the host CPU. Mode 011 (ECP FIFO - Address/RLE) A data byte written to this address is placed in the FIFO and tagged as an ECP Address/RLE. The hardware at the ECP port transmits this byte to the peripheral automatically. The operation of this register is ony defined for the forward direction (direction is 0). Refer to the ECP Parallel Port Forward Timing Diagram, located in the Timing Diagrams section of this data sheet . Device Status Register (DSR) ADDRESS OFFSET = 01H The Status Port is located at an offset of '01H' from the base address. Bits 0 - 2 are not implemented as register bits, during a read of the Printer Status Register these bits are a low level. The bits of the Status Port are defined as follows: BIT 3 nFault The level on the nFault input is read by the CPU as bit 3 of the Device Status Register. BIT 4 Select The level on the Select input is read by the CPU as bit 4 of the Device Status Register. BIT 5 PError The level on the PError input is read by the CPU as bit 5 of the Device Status Register. Printer Status Register. BIT 6 nAck The level on the nAck input is read by the CPU as bit 6 of the Device Status Register. BIT 7 nBusy The complement of the level on the BUSY input is read by the CPU as bit 7 of the Device Status Register. SMSC SIO10N268 Page 123 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet Device Control Register (DCR) ADDRESS OFFSET = 02H The Control Register is located at an offset of '02H' from the base address. The Control Register is initialized to zero by the RESET input, bits 0 to 5 only being affected; bits 6 and 7 are hard wired low. BIT 0 STROBE - STROBE This bit is inverted and output onto the nSTROBE output. BIT 1 AUTOFD - AUTOFEED This bit is inverted and output onto the nAUTOFD output. A logic 1 causes the printer to generate a line feed after each line is printed. A logic 0 means no autofeed. BIT 2 nINIT - nINITIATE OUTPUT This bit is output onto the nINIT output without inversion. BIT 3 SELECTIN This bit is inverted and output onto the nSLCTIN output. A logic 1 on this bit selects the printer; a logic 0 means the printer is not selected. BIT 4 ackIntEn - INTERRUPT REQUEST ENABLE The interrupt request enable bit when set to a high level may be used to enable interrupt requests from the Parallel Port to the CPU due to a low to high transition on the nACK input. Refer to the description of the interrupt under Operation, Interrupts. BIT 5 DIRECTION If mode=000 or mode=010, this bit has no effect and the direction is always out regardless of the state of this bit. In all other modes, Direction is valid and a logic 0 means that the printer port is in output mode (write); a logic 1 means that the printer port is in input mode (read). BITS 6 and 7 during a read are a low level, and cannot be written. cFifo (Parallel Port Data FIFO) ADDRESS OFFSET = 400h Mode = 010 Bytes written or DMAed from the system to this FIFO are transmitted by a hardware handshake to the peripheral using the standard parallel port protocol. Transfers to the FIFO are byte aligned. This mode is only defined for the forward direction. ecpDFifo (ECP Data FIFO) ADDRESS OFFSET = 400H Mode = 011 Rev. 0.5 (03-24-05) Page 124 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet Bytes written or DMAed from the system to this FIFO, when the direction bit is 0, are transmitted by a hardware handshake to the peripheral using the ECP parallel port protocol. Transfers to the FIFO are byte aligned. Data bytes from the peripheral are read under automatic hardware handshake from ECP into this FIFO when the direction bit is 1. Reads or DMAs from the FIFO will return bytes of ECP data to the system. tFifo (Test FIFO Mode) ADDRESS OFFSET = 400H Mode = 110 Data bytes may be read, written or DMAed to or from the system to this FIFO in any direction. Data in the tFIFO will not be transmitted to the to the parallel port lines using a hardware protocol handshake. However, data in the tFIFO may be displayed on the parallel port data lines. The tFIFO will not stall when overwritten or underrun. If an attempt is made to write data to a full tFIFO, the new data is not accepted into the tFIFO. If an attempt is made to read data from an empty tFIFO, the last data byte is re-read again. The full and empty bits must always keep track of the correct FIFO state. The tFIFO will transfer data at the maximum ISA rate so that software may generate performance metrics. The FIFO size and interrupt threshold can be determined by writing bytes to the FIFO and checking the full and serviceIntr bits. The writeIntrThreshold can be determined by starting with a full tFIFO, setting the direction bit to 0 and emptying it a byte at a time until serviceIntr is set. This may generate a spurious interrupt, but will indicate that the threshold has been reached. The readIntrThreshold can be determined by setting the direction bit to 1 and filling the empty tFIFO a byte at a time until serviceIntr is set. This may generate a spurious interrupt, but will indicate that the threshold has been reached. Data bytes are always read from the head of tFIFO regardless of the value of the direction bit. For example if 44h, 33h, 22h is written to the FIFO, then reading the tFIFO will return 44h, 33h, 22h in the same order as was written. cnfgA (Configuration Register A) ADDRESS OFFSET = 400H Mode = 111 This register is a read only register. When read, 10H is returned. This indicates to the system that this is an 8-bit implementation. (PWord = 1 byte) cnfgB (Configuration Register B) ADDRESS OFFSET = 401H Mode = 111 BIT 7 compress This bit is read only. During a read it is a low level. This means that this chip does not support hardware RLE compression. It does support hardware de-compression! SMSC SIO10N268 Page 125 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet BIT 6 intrValue Returns the value of the interrupt to determine possible conflicts. BITS [5:3] Parallel Port IRQ (read-only) Refer to Table 8.46. BITS [2:0] Parallel Port DMA (read-only) Refer to Table 8.47. ecr (Extended Control Register) ADDRESS OFFSET = 402H Mode = all This register controls the extended ECP parallel port functions. BITS 7,6,5 These bits are Read/Write and select the Mode. BIT 4 nErrIntrEn Read/Write (Valid only in ECP Mode) 1: 0: Disables the interrupt generated on the asserting edge of nFault. Enables an interrupt pulse on the high to low edge of nFault. Note that an interrupt will be generated if nFault is asserted (interrupting) and this bit is written from a 1 to a 0. This prevents interrupts from being lost in the time between the read of the ecr and the write of the ecr. BIT 3 dmaEn Read/Write 1: 0: Enables DMA (DMA starts when serviceIntr is 0). Disables DMA unconditionally. BIT 2 serviceIntr Read/Write 1: Disables DMA and all of the service interrupts. 0: Enables one of the following 3 cases of interrupts. Once one of the 3 service interrupts has occurred serviceIntr bit shall be set to a 1 by hardware. It must be reset to 0 to re-enable the interrupts. Writing this bit to a 1 will not cause an interrupt. case dmaEn=1: During DMA (this bit is set to a 1 when terminal count is reached). Rev. 0.5 (03-24-05) Page 126 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet case dmaEn=0 direction=0: This bit shall be set to 1 whenever there are writeIntrThreshold or more bytes free in the FIFO. case dmaEn=0 direction=1: This bit shall be set to 1 whenever there are readIntrThreshold or more valid bytes to be read from the FIFO. BIT 1 full Read only 1: 0: The FIFO cannot accept another byte or the FIFO is completely full. The FIFO has at least 1 free byte. BIT 0 empty Read only 1: 0: The FIFO is completely empty. The FIFO contains at least 1 byte of data. Table 8.45 - Extended Control Register R/W 000: MODE Standard Parallel Port Mode . In this mode the FIFO is reset and common drain drivers are used on the control lines (nStrobe, nAutoFd, nInit and nSelectIn). Setting the direction bit will not tri-state the output drivers in this mode. PS/2 Parallel Port Mode. Same as above except that direction may be used to tri-state the data lines and reading the data register returns the value on the data lines and not the value in the data register. All drivers have active pull-ups (push-pull). Parallel Port FIFO Mode. This is the same as 000 except that bytes are written or DMAed to the FIFO. FIFO data is automatically transmitted using the standard parallel port protocol. Note that this mode is only useful when direction is 0. All drivers have active pull-ups (push-pull). ECP Parallel Port Mode. In the forward direction (direction is 0) bytes placed into the ecpDFifo and bytes written to the ecpAFifo are placed in a single FIFO and transmitted automatically to the peripheral using ECP Protocol. In the reverse direction (direction is 1) bytes are moved from the ECP parallel port and packed into bytes in the ecpDFifo. All drivers have active pull-ups (push-pull). Selects EPP Mode: In this mode, EPP is selected if the EPP supported option is selected in configuration register CR04 (Bits[1,0] and Bit[6]). All drivers have active pull-ups (push-pull). Reserved Test Mode. In this mode the FIFO may be written and read, but the data will not be transmitted on the parallel port. All drivers have active pull-ups (push-pull). Configuration Mode. In this mode the confgA, confgB registers are accessible at 0x400 and 0x401. All drivers have active pull-ups (push-pull). 001: 010: 011: 100: 101: 110: 111: SMSC SIO10N268 Page 127 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet Table 8.46 - Extended Control Register (continued) IRQ SELECTED 15 14 11 10 cnfgB BITS [5:3] 110 101 100 011 Table 8.47 - Extended Control Register (continued) DMA SELECTED 3 2 1 All Others cnfgB BITS [2:0] 011 010 001 000 8.10.7 Operation 8.10.7.1 Mode Switching/Software Control Software will execute P1284 negotiation and all operation prior to a data transfer phase under programmed I/O control (mode 000 or 001). Hardware provides an automatic control line handshake, moving data between the FIFO and the ECP port only in the data transfer phase (modes 011 or 010). Setting the mode to 011 or 010 will cause the hardware to initiate data transfer. If the port is in mode 000 or 001 it may switch to any other mode. If the port is not in mode 000 or 001 it can only be switched into mode 000 or 001. The direction can only be changed in mode 001. 8.10.7.2 ECP Operation Prior to ECP operation the Host must negotiate on the parallel port to determine if the peripheral supports the ECP protocol. This is a somewhat complex negotiation carried out under program control in mode 000. After negotiation, it is necessary to initialize some of the port bits. The following are required: Set Set Set Set Direction = 0, enabling the drivers. strobe = 0, causing the nStrobe signal to default to the deasserted state. autoFd = 0, causing the nAutoFd signal to default to the deasserted state. mode = 011 (ECP Mode) ECP address/RLE bytes or data bytes may be sent automatically by writing the ecpAFifo or ecpDFifo respectively. NOTE: All FIFO data transfers are byte wide and byte aligned. Address/RLE transfers are byte-wide and only allowed in the forward direction. The host may switch directions by first switching to mode = 001, negotiating for the forward or reverse channel, setting direction to 1 or 0, then setting mode = 011. When direction is 1 the hardware shall Rev. 0.5 (03-24-05) Page 128 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet handshake for each ECP read data byte and attempt to fill the FIFO. Bytes may then be read from the ecpDFifo as long as it is not empty. ECP transfers may also be accomplished (albeit slowly) by handshaking individual bytes under program control in mode = 001, or 000. 8.10.7.3 Termination from ECP Mode Termination from ECP Mode is similar to the termination from Nibble/Byte Modes. The host is permitted to terminate from ECP Mode only in specific well-defined states. The termination can only be executed while the bus is in the forward direction. To terminate while the channel is in the reverse direction, it must first be transitioned into the forward direction. 8.10.7.4 Command/Data ECP Mode supports two advanced features to improve the effectiveness of the protocol for some applications. The features are implemented by allowing the transfer of normal 8 bit data or 8 bit commands. When in the forward direction, normal data is transferred when HostAck is high and an 8 bit command is transferred when HostAck is low. The most significant bit of the command indicates whether it is a run-length count (for compression) or a channel address. When in the reverse direction, normal data is transferred when PeriphAck is high and an 8 bit command is transferred when PeriphAck is low. The most significant bit of the command is always zero. Reverse channel addresses are seldom used and may not be supported in hardware. Table 8.48 - Forward Channel Commands (HostAck Low), Reverse Channel Commands (PeripAck Low) D7 0 1 D[6:0] Run-Length Count (0-127) (mode 0011 0X00 only) Channel Address (0-127) 8.10.7.5 Data Compression The ECP port supports run length encoded (RLE) decompression in hardware and can transfer compressed data to a peripheral. Run length encoded (RLE) compression in hardware is not supported. To transfer compressed data in ECP mode, the compression count is written to the ecpAFifo and the data byte is written to the ecpDFifo. Compression is accomplished by counting identical bytes and transmitting an RLE byte that indicates how many times the next byte is to be repeated. Decompression simply intercepts the RLE byte and repeats the following byte the specified number of times. When a run-length count is received from a peripheral, the subsequent data byte is replicated the specified number of times. A run-length count of zero specifies that only one byte of data is represented by the next data byte, whereas a run-length count of 127 indicates that the next byte should be expanded to 128 bytes. To prevent data expansion, however, run-length counts of zero should be avoided. SMSC SIO10N268 Page 129 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet 8.10.7.6 Pin Definition The drivers for nStrobe, nAutoFd, nInit and nSelectIn are open-drain in mode 000 and are push-pull in all other modes. 8.10.7.7 LPC Connections The interface can never stall causing the host to hang. The width of data transfers is strictly controlled on an I/O address basis per this specification. All FIFO-DMA transfers are byte wide, byte aligned and end on a byte boundary. (The PWord value can be obtained by reading Configuration Register A, cnfgA, described in the next section). Single byte wide transfers are always possible with standard or PS/2 mode using program control of the control signals. 8.10.7.8 Interrupts The interrupts are enabled by serviceIntr in the ecr register. serviceIntr = 1 Disables the DMA and all of the service interrupts. serviceIntr = 0 Enables the selected interrupt condition. If the interrupting condition is valid, then the interrupt is generated immediately when this bit is changed from a 1 to a 0. This can occur during Programmed I/O if the number of bytes removed or added from/to the FIFO does not cross the threshold. An interrupt is generated when: 1) 2) For DMA transfers: When serviceIntr is 0, dmaEn is 1 and the DMA TC cycle is received. For Programmed I/O: a) When serviceIntr is 0, dmaEn is 0, direction is 0 and there are writeIntrThreshold or more free bytes in the FIFO. Also, an interrupt is generated when serviceIntr is cleared to 0 whenever there are writeIntrThreshold or more free bytes in the FIFO. b) When serviceIntr is 0, dmaEn is 0, direction is 1 and there are readIntrThreshold or more bytes in the FIFO. Also, an interrupt is generated when serviceIntr is cleared to 0 whenever there are readIntrThreshold or more bytes in the FIFO. 3) When nErrIntrEn is 0 and nFault transitions from high to low or when nErrIntrEn is set from 1 to 0 and nFault is asserted. When ackIntEn is 1 and the nAck signal transitions from a low to a high. 4) 8.10.7.9 FIFO Operation The FIFO threshold is set in the chip configuration registers. All data transfers to or from the parallel port can proceed in DMA or Programmed I/O (non-DMA) mode as indicated by the selected mode. The FIFO is used by selecting the Parallel Port FIFO mode or ECP Parallel Port Mode. (FIFO test mode will be addressed separately.) After a reset, the FIFO is disabled. Each data byte is transferred by a Programmed I/O cycle or DMA cycle depending on the selection of DMA or Programmed I/O mode. The following paragraphs detail the operation of the FIFO flow control. In these descriptions, Rev. 0.5 (03-24-05) Page 130 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet A low threshold value (i.e. 2) results in longer periods of time between service requests, but requires faster servicing of the request for both read and write cases. The host must be very responsive to the service request. This is the desired case for use with a "fast" system. A high value of threshold (i.e. 12) is used with a "sluggish" system by affording a long latency period after a service request, but results in more frequent service requests. 8.10.7.10 DMA Transfers DMA transfers are always to or from the ecpDFifo, tFifo or CFifo. DMA utilizes the standard PC DMA services. To use the DMA transfers, the host first sets up the direction and state as in the programmed I/O case. Then it programs the DMA controller in the host with the desired count and memory address. Lastly it sets dmaEn to 1 and serviceIntr to 0. The ECP requests DMA transfers from the host by encoding the LDRQ# pin. The DMA will empty or fill the FIFO using the appropriate direction and mode. When the terminal count in the DMA controller is reached, an interrupt is generated and serviceIntr is asserted, disabling DMA. In order to prevent possible blocking of refresh requests a DMA cycle shall not be requested for more than 32 DMA cycles in a row. The FIFO is enabled directly by the host initiating a DMA cycle for the requested channel, and addresses need not be valid. An interrupt is generated when a TC cycle is received. (Note: The only way to properly terminate DMA transfers is with a TC cycle.) DMA may be disabled in the middle of a transfer by first disabling the host DMA controller. Then setting serviceIntr to 1, followed by setting dmaEn to 0, and waiting for the FIFO to become empty or full. Restarting the DMA is accomplished by enabling DMA in the host, setting dmaEn to 1, followed by setting serviceIntr to 0. 8.10.7.11 DMA Mode - Transfers from the FIFO to the Host NOTE: In the reverse mode, the peripheral may not continue to fill the FIFO if it runs out of data to transfer, even if the chip continues to request more data from the peripheral. The ECP requests a DMA cycle whenever there is data in the FIFO. The DMA controller responds to the request by reading data from the FIFO. The ECP stop requesting DMA cycles when the FIFO becomes empty or when a TC cycle is received, indicating that no more data is required. If the ECP stops requesting DMA cycles due to the FIFO going empty, then a DMA cycle is requested again as soon as there is one byte in the FIFO. If the ECP stops requesting DMA cycles due to the TC cycle, then a DMA cycle is requested again when there is one byte in the FIFO, and serviceIntr has been re-enabled. 8.10.7.12 Programmed I/O Mode or Non-DMA Mode The ECP or parallel port FIFOs may also be operated using interrupt driven programmed I/O. Software can determine the writeIntrThreshold, readIntrThreshold, and FIFO depth by accessing the FIFO in Test Mode. Programmed I/O transfers are to the ecpDFifo at 400H and ecpAFifo at 000H or from the ecpDFifo located at 400H, or to/from the tFifo at 400H. To use the programmed I/O transfers, the host first sets up the direction and state, sets dmaEn to 0 and serviceIntr to 0. The ECP requests programmed I/O transfers from the host by activating the interrupt. The programmed I/O will empty or fill the FIFO using the appropriate direction and mode. NOTE: A threshold of 16 is equivalent to a threshold of 15. These two cases are treated the same. 8.10.7.13 Programmed I/O - Transfers from the FIFO to the Host In the reverse direction an interrupt occurs when serviceIntr is 0 and readIntrThreshold bytes are available in the FIFO. If at this time the FIFO is full it can be emptied completely in a single burst, otherwise readIntrThreshold bytes may be read from the FIFO in a single burst. SMSC SIO10N268 Page 131 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet readIntrThreshold =(16- 8.10.7.14 Programmed I/O - Transfers from the Host to the FIFO In the forward direction an interrupt occurs when serviceIntr is 0 and there are writeIntrThreshold or more bytes free in the FIFO. At this time if the FIFO is empty it can be filled with a single burst before the empty bit needs to be re-read. Otherwise it may be filled with writeIntrThreshold bytes. writeIntrThreshold = (16- An interrupt is generated when serviceIntr is 0 and the number of bytes in the FIFO is less than or equal to 8.10.8 Parallel Port Floppy Disk Controller The Floppy Disk Control signals are available optionally on the parallel port pins. When this mode is selected, the parallel port is not available. There are two modes of operation, PPFD1 and PPFD2. These modes can be selected in the Parallel and Serial Extended Setup Register (CR04). PPFD1 has only drive 1 on the parallel port pins; PPFD2 has drive 0 and 1 on the parallel port pins. See the Configuration section for description of the register. The FDC_PP pin can be used to switch the parallel port pins between the FDC and the parallel port functions. See the following sub-section. The following parallel port pins are read as follows by a read of the parallel port register: 1) 2) 3) Data Register (read) = last Data Register (write) Control Register read as "cable not connected" STROBE, AUTOFD and SLC = 0 and nINIT =1 Status Register reads: nBUSY = 0, PE = 0, SLCT = 0, nACK = 1, nERR = 1 The following FDC pins are all in the high impedence state when the PPFDC is actually selected by the drive select register: 1) 2) nWDATA, DENSEL, nHDSEL, nWGATE, nDIR, nSTEP, nDS1, nDS0, nMTR0, nMTR1. If PPFDx is selected, then the parallel port can not be used as a parallel port until "Normal" mode is selected. The FDC signals are muxed onto the Parallel Port pins as shown in Table 8.50. For ACPI compliance the FDD pins that are multiplexed onto the Parallel Port function independently of the state of the Parallel Port controller. For example, if the FDC is enabled onto the Parallel Port the multiplexed FDD interface functions normally regardless of the Parallel Port Power control, CR01.2. Table 8.49 illustrates this functionality. Rev. 0.5 (03-24-05) Page 132 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet Table 8.49 - Modified Parallel Port FDD Control PARALLEL PORT POWER CR01.2 1 0 X Note 8.36 0 0 1 X PARALLEL PORT FDC CONTROL CR04.3 CR04.2 0 0 X 1 PARALLEL PORT FDC STATE OFF OFF ON PARALLEL PORT STATE ON OFF OFF Note 8.36 The Parallel Port Control register reads as "Cable Not Connected" when the Parallel Port FDC is enabled; i.e., STROBE = AUTOFD = SLC = 0 and nINIT = 1. Table 8.50 - FDC Parallel Port Pins CONNECTOR PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Note 8.37 QFP CHIP PIN # 81 65 66 67 68 69 71 72 73 78 77 76 75 80 79 63 64 SPP MODE nSTROBE PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 nACK BUSY PE SLCT nALF nERROR nINIT nSLCTIN PIN DIRECTION I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I I I/O I I/O I/O FDC MODE (nDS0) nINDEX nTRK0 nWP nRDATA nDSKCHG (nMTR0) nDS1 nMTR1 nWDATA nWGATE DRVDEN0 nHDSEL nDIR nSTEP PIN DIRECTION I/(O) Note 8.37 I I I I I I/(O) Note 8.37 O O O O O O O O These pins are outputs in mode PPFD2, inputs in mode PPFD1. 8.10.8.1 FDC on Parallel Port Pin The "floppy on the parallel port" pin function, FDC_PP, is muxed onto GP11. This pin function can be used to switch the parallel port pins between the FDC and the parallel port. The FDC_PP pin can generate a PME and an SMI by enabling GP11 in the appropriate PME and SMI enable registers (bit[1] of PME_EN1 and bit[1] of SMI_EN1 - see the Runtime Registers section). This pin generates an SMI and PME on both a low-to-high and a high-to-low edge. The pin function for GP11 is selectable in the GPIO Alternate Function Select register 1 located at offset CR44. GPIO Polarity Register 1 at offset CR32 controls the polarity of the GP11 pin. When the FDC_PP function is selected, the pin must also be selected as an input via bit[1] of the GPIO Direction Register 1 located at offset CR31. If the Floppy_PP bits, CR21 bits[1:0] = 01 or 10, and the FDC_PP function is selected on GP11, then the default functionality (non-inverted polarity) for this pin is as follows: when the pin is low, the parallel port SMSC SIO10N268 Page 133 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet pins are used for a floppy disk controller; when the pin is high, the parallel port pins are used for a parallel port. The polarity bit controls the state of the pin. If the Floppy_PP bits, CR21 bits[1:0]=00 then the pin is not used to switch the parallel port pins between the FDC and the parallel port, even if the FDC_PP function is selected on GP11. See the Configuration section for register description. NOTE: When the floppy is selected on the parallel port, the parallel port IRQ, SMI and the parallel port DRQ will not come out of the part. 8.11 Watchdog Timer The SIO10N268's Watchdog Timer (WDT) has a programmable time-out ranging from 1 to 255 minutes with one minute resolution, or 1 to 255 seconds with 1 second resolution. The units of the WDT timeout value are selected via bit[7] of the WDT_TIMEOUT register (Runtime Register at offset 0x11). The WDT time-out value is set through the WDT_VAL Runtime register. Setting the WDT_VAL register to 0x00 disables the WDT function (this is its power on default). Setting the WDT_VAL to any other non-zero value will cause the WDT to reload and begin counting down from the value loaded. When the WDT count value reaches zero the counter stops and sets the Watchdog time-out status bit in the WDT_CTRL Runtime register. Note: Regardless of the current state of the WDT, the WDT time-out status bit can be directly set or cleared by the Host CPU. The Watchdog Timer may be configured to generate an interrupt on the rising edge of the Time-out status bit. This interrupt can be used to generate an IO_PME#, an IO_SMI#, a signal on the WDT output pin, or it may be mapped onto the Serial IRQ stream. The following list describes the registers used to enable these events. NOTE: NOTE: The WDT, PME, and SMI registers are located in the Runtime Register block. The WDT defaults to generating an active high signal. The polarity of this output may be inverted to generate an active low signal through bit[1] GP21 located in GPIO Polarity Register 2 at offset CR34. Four methods of enabling Watchdog Timer interrupt events: 1) The WDT can generate an IO_PME#. If a watchdog timer event occurs the WDT status bit in the PME_STS2 register at offset 0x03 will be set. If bit[0] PME_En in the PME_En registers at offset 0x01 is set to `1' and bit[7] WDT in the PME_EN2 register at offset 0x06 is set to `1' an interrupt will be generated on the IO_PME# pin. The WDT can generate an IO_SMI#. If a watchdog timer event occurs the WDT status bit in the SMI_STS3 register at offset 0x18 will be set. If bits[5:4] GP12 Alternate Function Select in the GPIO Alternate Function Select Register 1 at offset CR44 are set to `01' and bit[0]EN_WDT in the SMI_EN3 at offset 0x19 is set to `1' an interrupt will be generated on the IO_SMI# pin. The WDT can generate a signal on the GP21/IRTX2/WDT pin. If a watchdog timer event occurs and bits[3:2] GP21 Alternate Function Select in the GPIO Alternate Function Select Register 3 at offset CR46 are set to `10' an interrupt will be generated on the WDT pin. The WDT can generate an interrupt on the Serial IRQ stream. If a watchdog timer event occurs and bits[7:4] WDT Interrupt Mapping located in the WDT_CFG register at offset 0x13 are programmed to a value other than `0000' an interrupt will be generated on the SER_IRQ output pin. See section 8.14 Serial IRQ on page 138 for a description of generating interrupts on the SER_IRQ pin. 2) 3) 4) The host may force a Watchdog time-out to occur by writing a "1" to bit 2 of the WDT_CTRL (Force WD Time-out) Runtime register. Writing a "1" to this bit forces the WDT count value to zero and sets bit 0 of the WDT_CTRL (Watchdog Status). Bit 2 of the WDT_CTRL is self-clearing. See Chapter 9 Runtime Registers for description of these registers. Rev. 0.5 (03-24-05) Page 134 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet 8.12 LED Functionality The SIO10N268 provides LED functionality on two pins: GP13/IRQIN1/LED1 GP23/LED2/IRQIN2 The LED logic and supporting registers are powered by VTR. The LED1 pin is powered by VCC and the LED2 pin is powered by VTR. These pins can be configured to turn an LED on and off and blink independent of each other through the LED1 and LED2 runtime registers at offset 0x15 and 0x16, when the device is powered by VCC. See section Chapter 9 Runtime Registers for a description of these registers. The LED2 pin (GP23) is capable of controlling an LED while the device is under VTR power with VCC removed. In order to control an LED while the part is under VTR power, the GPIO pin must have been configured for the LED2 function while the device was powered by VCC. NOTE: The LED2 pin will not support the blink function under VTR power (VCC removed) if an external 32kHz clock source is not connected. LED1 and LED2 may be configured for either open drain or push-pull buffer type. In the case of opendrain buffer type, the pin is capable of sinking current to control the LED. In the case of push-pull buffer type the part will source current. NOTE: 8.13 Power Management Power management capabilities are provided for the following logical devices: floppy disk, UART 1, UART 2, UART 3, UART 4, and the parallel port. For each logical device, two types of power management are provided: direct powerdown and auto powerdown. 8.13.1 FDC Power Management Direct power management is controlled by Bit[3] in CR00. Refer to the Configuration section for more information. Auto Power Management is enabled by Bit[7] in CR07. When set, this bit allows FDC to enter powerdown when all of the following conditions have been met: 1) 2) 3) 4) The motor enable pins of register 3F2H are inactive (zero). The part must be idle; MSR=80H and INT = 0 (INT may be high even if MSR = 80H due to polling interrupts). The head unload timer must have expired. The Auto powerdown timer (10msec) must have timed out. An internal timer is initiated as soon as the auto powerdown command is enabled. The part is then powered down when all the conditions are met. Disabling the auto powerdown mode cancels the timer and holds the FDC block out of auto powerdown. NOTE: At least 8us delay should be added when exiting FDC Auto Powerdown mode. If the operating environment is such that this delay cannot be guaranteed, the auto powerdown mode should not be used and Direct powerdown mode should be used instead. The Direct powerdown mode requires at least 8us delay at 250K bits/sec configuration and 4us delay at 500K bits/sec. The delay should be added so that the internal microcontroller can prepare itself to accept commands. See SMSC SIO10N268 Page 135 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet SMSC Application Note: Application Considerations When Using the Powerdown Feature of SMSC Floppy Disk Controllers. 8.13.1.1 DSR From Powerdown If DSR powerdown is used when the part is in auto powerdown, the DSR powerdown will override the auto powerdown. However, when the part is awakened from DSR powerdown, the auto powerdown will once again become effective. 8.13.1.2 Wake Up From Auto Powerdown If the part enters the powerdown state through the auto powerdown mode, then the part can be awakened by reset or by appropriate access to certain registers. If a hardware or software reset is used then the part will go through the normal reset sequence. If the access is through the selected registers, then the FDC resumes operation as though it was never in powerdown. Besides activating the PCI_RESET# pin or one of the software reset bits in the DOR or DSR, the following register accesses will wake up the part: 1) 2) 3) Enabling any one of the motor enable bits in the DOR register (reading the DOR does not awaken the part). A read from the MSR register. A read or write to the Data register. Once awake, the FDC will reinitiate the auto powerdown timer for 10 ms. The part will powerdown again when all the powerdown conditions are satisfied. 8.13.1.3 Register Behavior Table 8.51 illustrates the AT and PS/2 (including Model 30) configuration registers available and the type of access permitted. In order to maintain software transparency, access to all the registers must be maintained. As Table 8.51 shows, two sets of registers are distinguished based on whether their access results in the part remaining in powerdown state or exiting it. Access to all other registers is possible without awakening the part. These registers can be accessed during powerdown without changing the status of the part. A read from these registers will reflect the true status as shown in the register description in the FDC description. A write to the part will result in the part retaining the data and subsequently reflecting it when the part awakens. Accessing the part during powerdown may cause an increase in the power consumption by the part. The part will revert back to its low power mode when the access has been completed. 8.13.1.4 Pin Behavior The SIO10N268 is specifically designed for systems in which power conservation is a primary concern. This makes the behavior of the pins during powerdown very important. The pins of the SIO10N268 can be divided into two major categories: system interface and floppy disk drive interface. The floppy disk drive pins are disabled so that no power will be drawn through the part as a result of any voltage applied to the pin within the part's power supply range. Most of the system interface pins are left active to monitor system accesses that may wake up the part. Rev. 0.5 (03-24-05) Page 136 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet Table 8.51 - PC/AT and PS/2 Available Registers AVAILABLE REGISTERS BASE + ADDRESS PC-AT PS/2 (MODEL ACCESS 30) PERMITTED Access to these registers DOES NOT wake up the part 00H ---SRA R 01H ---SRB R 02H R/W DOR (Note 8.38) DOR (Note 8.38) 03H ------04H W DSR (Note 8.38) DSR (Note 8.38) 06H ------07H DIR DIR R 07H CCR CCR W Access to these registers wakes up the part 04H MSR MSR R 05H Data Data R/W Note 8.38 Writing to the DOR or DSR does not wake up the part, however, writing any of the motor enable bits or doing a software reset (via DOR or DSR reset bits) will wake up the part. 8.13.1.5 System Interface Pins Neither the LPC or ISA interface pins are effected by the direct powerdown or auto powerdown states. 8.13.1.6 FDD Interface Pins All pins in the FDD interface which can be connected directly to the floppy disk drive itself are either DISABLED or TRISTATED. Pins used for local logic control or part programming are unaffected. Table 8.52 depicts the state of the floppy disk drive interface pins in the powerdown state. Table 8.52 - State of Floppy Disk Drive Interface Pins in Powerdown FDD PINS nRDATA nWRTPRT nTRK0 nINDEX nDSKCHG OUTPUT PINS nMTR0 nDS0 nDIR nSTEP nWDATA nWGATE nHDSEL Tristated Tristated Tristated Tristated Tristated Tristated Tristated STATE IN AUTO POWERDOWN INPUT PINS Input Input Input Input Input SMSC SIO10N268 Page 137 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet FDD PINS DRVDEN[0:1] STATE IN AUTO POWERDOWN Tristated 8.13.2 UART Power Management Direct power management is controlled by CR02. Refer to the Configuration section for more information. Auto Power Management may be enabled by the UART1, UART2, UART3, or UART4 enable bits in CR07. When set, these bits allow the following auto power management operations: 1) 2) The transmitter enters auto powerdown when the transmit buffer and shift register are empty. The receiver enters powerdown when the following conditions are all met: a) b) NOTE: Receive FIFO is empty The receiver is waiting for a start bit. While in powerdown the Ring Indicator interrupt is still valid and transitions when the RI input changes. 8.13.2.1 Exit Auto Powerdown The transmitter exits powerdown on a write to the XMIT buffer. The receiver exits auto powerdown when RXDx changes state. 8.13.3 Parallel Port Direct power management is controlled by Bit[2] in CR01. Refer to the Configuration section for more information. Auto Power Management is enabled by Bit[4] in CR07. When set, this bit allows the ECP or EPP logical parallel port blocks to be placed into powerdown when not being used. The EPP logic is in powerdown under any of the following conditions: 1) 2) EPP is not enabled in the configuration registers. EPP is not selected through ecr while in ECP mode. The ECP logic is in powerdown under any of the following conditions: 1) 2) ECP is not enabled in the configuration registers. SPP, PS/2 Parallel port or EPP mode is selected through ecr while in ECP mode. 8.13.3.1 Exit Auto Powerdown The parallel port logic can change powerdown modes when the ECP mode is changed through the ecr register or when the parallel port mode is changed through the configuration registers. 8.14 Serial IRQ The SIO10N268 supports the serial interrupt to transmit interrupt information to the host system. The serial interrupt scheme adheres to the Serial IRQ Specification for PCI Systems, Version 6.0. The PCI_CLK, SER_IRQ and nCLKRUN pins are used for this interface. The Serial IRQ/CLKRUN Enable bit D7 in CR29 activates the serial interrupt interface. Rev. 0.5 (03-24-05) Page 138 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet 8.14.1 Timing Diagrams For SER_IRQ Cycle a) Start Frame timing with source sampled a low pulse on IRQ1 SL or START FRAME H R T IRQ0 FRAME IRQ1 FRAME IRQ2 FRAME S R T S R T S R T H PCI_CLK SER_IRQ Drive Source NOTE: Note 8.39 a) IRQ START Host Controller None IRQ1 None H=Host Control; R=Recovery; T=Turn-Around; SL=Slave Control; S=Sample Start Frame pulse can be 4-8 clocks wide depending on the location of the device in the PCI bridge hierarchy in a synchronous bridge design. Stop Frame Timing with Host using 17 SER_IRQ sampling period. IRQ14 FRAME SRT PCI_CLK SER_IRQ Driver NOTE: Note 8.40 Note 8.41 Note 8.42 IRQ15 FRAME SRT IOCHCK# FRAME SRT STOP FRAME NEXT CYCLE T I H R STOP None IRQ15 None Host Controller START H=Host Control; R=Recovery; T=Turn-Around; S=Sample; I=Idle Stop pulse is 2 clocks wide for Quiet mode, 3 clocks wide for Continuous mode. There may be none, one or more Idle states during the Stop Frame. The next SER_IRQ cycle's Start Frame pulse may or may not start immediately after the turn-around clock of the Stop Frame. 8.14.1.1 SER_IRQ Cycle Control There are two modes of operation for the SER_IRQ Start Frame. 1) Quiet (Active) Mode: Any device may initiate a Start Frame by driving the SER_IRQ low for one clock, while the SER_IRQ is Idle. After driving low for one clock the SER_IRQ is immediately tri-stated without at any time driving high. A Start Frame may not be initiated while the SER_IRQ is Active. The SER_IRQ is Idle between Stop and Start Frames. The SER_IRQ is Active between Start and Stop Frames. This mode of operation allows the SER_IRQ to be Idle when there are no IRQ/Data transitions which should be most of the time. SMSC SIO10N268 Page 139 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet Once a Start Frame has been initiated the Host Controller will take over driving the SER_IRQ low in the next clock and will continue driving the SER_IRQ low for a programmable period of three to seven clocks. This makes a total low pulse width of four to eight clocks. Finally, the Host Controller will drive the SER_IRQ back high for one clock, then tri-state. Any SER_IRQ Device (i.e., The SIO10N268) which detects any transition on an IRQ/Data line for which it is responsible must initiate a Start Frame in order to update the Host Controller unless the SER_IRQ is already in an SER_IRQ Cycle and the IRQ/Data transition can be delivered in that SER_IRQ Cycle. 2) Continuous (Idle) Mode: Only the Host controller can initiate a Start Frame to update IRQ/Data line information. All other SER_IRQ agents become passive and may not initiate a Start Frame. SER_IRQ will be driven low for four to eight clocks by Host Controller. This mode has two functions. It can be used to stop or idle the SER_IRQ or the Host Controller can operate SER_IRQ in a continuous mode by initiating a Start Frame at the end of every Stop Frame. An SER_IRQ mode transition can only occur during the Stop Frame. Upon reset, SER_IRQ bus is defaulted to Continuous mode, therefore only the Host controller can initiate the first Start Frame. Slaves must continuously sample the Stop Frames pulse width to determine the next SER_IRQ Cycle's mode. 8.14.1.2 SER_IRQ Data Frame Once a Start Frame has been initiated, the SIO10N268 will watch for the rising edge of the Start Pulse and start counting IRQ/Data Frames from there. Each IRQ/Data Frame is three clocks: Sample phase, Recovery phase, and Turn-around phase. During the Sample phase the SIO10N268 drives the SER_IRQ low, if and only if, its last detected IRQ/Data value was low. If its detected IRQ/Data value is high, SER_IRQ is left tri-stated. During the Recovery phase the SIO10N268 drives the SER_IRQ high, if and only if, it had driven the SER_IRQ low during the previous Sample Phase. During the Turn-around Phase the SIO10N268 tri-states the SER_IRQ. The SIO10N268 will drive the SER_IRQ line low at the appropriate sample point if its associated IRQ/Data line is low, regardless of which device initiated the Start Frame. The Sample Phase for each IRQ/Data follows the low to high transition of the Start Frame pulse by a number of clocks equal to the IRQ/Data Frame times three, minus one. (e.g. The IRQ5 Sample clock is the sixth IRQ/Data Frame, (6 x 3) - 1 = 17th clock after the rising edge of the Start Pulse). Table 8.53 - SER_IRQ Sampling Periods SER_IRQ PERIOD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SIGNAL SAMPLED Not Used IRQ1 IO_SMI#/IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 # OF CLOCKS PAST START 2 5 8 11 14 17 20 23 26 29 32 35 38 41 44 Rev. 0.5 (03-24-05) Page 140 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet SER_IRQ PERIOD 16 SIGNAL SAMPLED IRQ15 # OF CLOCKS PAST START 47 The SER_IRQ data frame supports IRQ2 from a logical device on Period 3, which can be used for the System Management Interrupt (nSMI). When using Period 3 for IRQ2 the user should mask off the SMI via the SMI Enable Register. Likewise, when using Period 3 for nSMI the user should not configure any logical devices as using IRQ2. SER_IRQ Period 14 is used to transfer IRQ13. Logical devices FDC, Parallel Port, Serial Port 1, Serial Port 2, Serial Port 3, Serial Port 4, and WDT have IRQ13 as a choice for their primary interrupt. The SMI is enabled onto the SMI frame of the Serial IRQ via bit 6 of SMI Enable Register 2 and onto the IO_SMI# pin via bit 7 of the SMI Enable Register 2. The following devices may be mapped into the Serial IRQ stream. FDC Parallel Port Serial Port 1 Serial Port 2 Serial Port 3 Serial Port 4 WDT 8.14.1.3 Stop Cycle Control Once all IRQ/Data Frames have completed the Host Controller will terminate SER_IRQ activity by initiating a Stop Frame. Only the Host Controller can initiate the Stop Frame. A Stop Frame is indicated when the SER_IRQ is low for two or three clocks. If the Stop Frame's low time is two clocks then the next SER_IRQ Cycle's sampled mode is the Quiet mode; and any SER_IRQ device may initiate a Start Frame in the second clock or more after the rising edge of the Stop Frame's pulse. If the Stop Frame's low time is three clocks then the next SER_IRQ Cycle's sampled mode is the Continuos mode; and only the Host Controller may initiate a Start Frame in the second clock or more after the rising edge of the Stop Frame's pulse. 8.14.1.4 Latency Latency for IRQ/Data updates over the SER_IRQ bus in bridge-less systems with the minimum Host supported IRQ/Data Frames of seventeen, will range up to 96 clocks (3.84S with a 25MHz PCI Bus or 2.88uS with a 33MHz PCI Bus). If one or more PCI to PCI Bridge is added to a system, the latency for IRQ/Data updates from the secondary or tertiary buses will be a few clocks longer for synchronous buses, and approximately double for asynchronous buses. 8.14.1.5 EOI/ISR Read Latency Any serialized IRQ scheme has a potential implementation issue related to IRQ latency. IRQ latency could cause an EOI or ISR Read to precede an IRQ transition that it should have followed. This could cause a system fault. The host interrupt controller is responsible for ensuring that these latency issues are mitigated. The recommended solution is to delay EOIs and ISR Reads to the interrupt controller by the same amount as the SER_IRQ Cycle latency in order to ensure that these events do not occur out of order. SMSC SIO10N268 Page 141 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet 8.14.1.6 AC/DC Specification Issue All SER_IRQ agents must drive / sample SER_IRQ synchronously related to the rising edge of PCI bus clock. The SER_IRQ pin uses the electrical specification of PCI bus. Electrical parameters will follow PCI spec. section 4, sustained tri-state. 8.14.1.7 Reset and Initialization The SER_IRQ bus uses PCI_RESET# as its reset signal. The SER_IRQ pin is tri-stated by all agents while PCI_RESET# is active. With reset, SER_IRQ Slaves are put into the (continuous) IDLE mode. The Host Controller is responsible for starting the initial SER_IRQ Cycle to collect system's IRQ/Data default values. The system then follows with the Continuous/Quiet mode protocol (Stop Frame pulse width) for subsequent SER_IRQ Cycles. It is Host Controller's responsibility to provide the default values to 8259's and other system logic before the first SER_IRQ Cycle is performed. For SER_IRQ system suspend, insertion, or removal application, the Host controller should be programmed into Continuous (IDLE) mode first. This is to guarantee SER_IRQ bus is in IDLE state before the system configuration changes. 8.14.2 Routable IRQ Inputs The routable IRQ input (IRQINx) functions are on pins 53 (GP13/IRQIN1/LED1), 20 (GP23/nLED2/IRQIN2), and 60 (GP20/IRRX2/IRQIN3). The IRQINx pin's IRQ time slot in the Serial IRQ stream is selected via a 4-bit control register for each IRQIN function (CR29 for IRQIN1, CR2A for IRQIN2 and IRQIN3). A value of 0000 disables the IRQ function. NOTE: In order to use an IRQ for one of the IRQINx inputs that are muxed on the GPIO pins, the corresponding IRQ must not be used for any of the devices in the SIO10N268. Otherwise contention may occur. IRQIN1, IRQIN2, and IRQIN3 are capable of generating PME wake events. If an IRQINx pin generates an event, the associated PME Wake Status bit will be set to `1'. The following is a list of the PME status and enable bits associated with the IRQINx pins. IRQIN1 will generate an event on bit[3] GP13 of the PME_STS1 register at offset 0x02. If bit[3] GP13 of the PME_EN1 register at offset 0x05 is set to `1' and the PME_EN bit is set to `1' in the PME_EN register offset 0x01 the IO_PME# pin will be asserted. IRQIN2 will generate an event on bit[5] GP23 of the PME_STS2 register at offset 0x03. If bit[5] GP23 of the PME_EN2 register at offset 0x06 is set to `1' and the PME_EN bit is set to `1' in the PME_EN register offset 0x01 the IO_PME# pin will be asserted. IRQIN3 will generate an event on bit[2] GP20 of the PME_STS2 register at offset 0x03. If bit[2] GP20 of the PME_EN2 register at offset 0x06 is set to `1' and the PME_EN bit is set to `1' in the PME_EN register offset 0x01 the IO_PME# pin will be asserted. IRQIN1 and IRQIN2 are capable of generating SMI events. If an IRQINx pin generates an event, the associated SMI Status bit will be set to `1'. The following is a list of the SMI status and enable bits associated with the IRQINx pins. IRQIN1 will generate an event on bit[3] GP13 of the SMI_STS1 register at offset 0x08. If bit[3] GP13 of the SMI_EN1 register at offset 0x0A is set to `1' the IO_SMI# pin will be asserted. IRQIN2 will generate an event on bit[4] GP23 of the SMI_STS2 register at offset 0x09. If bit[4] GP23 of the SMI_EN2 register at offset 0x0B is set to `1' the IO_SMI# pin will be asserted. NOTE: IRQIN3 is not capable of generating an SMI event. The edge is programmable through the polarity bit of the GPIO control register. Application Note: If GPIO function is selected on GP13/IRQIN1, GP23/nLED2/IRQIN2, or GP20/IRRX2/IRQIN3 pins and if IRQ is selected using the routing registers (CR29 for IRQIN1 and CR2A for IRQIN2 and IRQIN3), IRQs will Rev. 0.5 (03-24-05) Page 142 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet be generated on the Serial IRQ stream. The state of the GPIO pins will be reflected on the serial IRQ stream. The IRQ selection bits should be `0000' in the IRQ routing registers when GPIO functions are used. These IRQ selection bits default to `0000' on VCC POR. 8.15 PCI CLKRUN Support 8.15.1 Overview The SIO10N268 supports the PCI CLKRUN# signal. CLKRUN# is used to indicate the PCI clock status as well as to request that a stopped clock be started. The SIO10N268 CLKRUN# signal is on pin number 28. See Figure 8.9 for an example of a typical system implementation using CLKRUN#. If the SIO10N268 SIRQ_CLKRUN_EN signal is disabled, it will disable the CLKRUN# support related to LDRQ# in addition to disabling the SER_IRQ and the CLKRUN# associated with SER_IRQ. CLKRUN# is an open drain output and an input. Refer to the PCI Mobile Design Guide Rev 1.0 for a description of the CLKRUN# function. 8.15.2 CLKRUN# for Serial IRQ The SIO10N268 supports the PCI CLKRUN# signal for the Serial IRQs. If an SIO interrupt occurs while the PCI clock is stopped, CLKRUN# is asserted before the serial interrupt signal is driven active. See section 8.15.4 Using CLKRUN# below for more details. 8.15.3 CLKRUN# for LDRQ# CLKRUN# support is also provided in the SIO10N268 for the LDRQ# signal. If a device requests DMA service while the PCI clock is stopped, CLKRUN# is asserted to restart the PCI clock. This is required to drive the LDRQ# signal active. See section 8.15.4 Using CLKRUN# below for more details. 8.15.4 Using CLKRUN# If CLKRUN# is sampled "high", the PCI clock is stopped or stopping. If CLKRUN# is sampled "low", the PCI clock is starting or started (running). If a device in the SIO10N268 asserts or de-asserts an interrupt or asserts a DMA request, and CLKRUN# is sampled "high", the SIO10N268 requests the restoration of the clock by asserting the CLKRUN# signal asynchronously (Table 8.54). The SIO10N268 holds CLKRUN# low until it detects two rising edges of the clock. After the second clock edge, the SIO10N268 disables the open drain driver (Figure 8.10). The SIO10N268 will not assert CLKRUN# under any conditions if SIRQ_CLKRUN_EN is inactive ("0"). The SIRQ_CLKRUN_EN bit is D7 in CR29. The SIO10N268 will not assert CLKRUN# if it is already driven low by the central resource; i.e., the PCI CLOCK GENERATOR in Figure 8.9. The SIO10N268 will not assert CLKRUN# unless the line has been deasserted for two successive clocks; i.e., before the clock was stopped (Figure 8.10). SMSC SIO10N268 Page 143 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet Table 8.54 - SIO10N268 CLKRUN# Function SIRQ_CLKRUN_EN 0 1 INTERNAL INTERRUPTS/ DMA REQUESTS X NO CHANGE CHANGE/ASSERTION (Note 8.43) CLKRUN# X X 0 1 ACTION None None None Assert CLKRUN# (Note 8.44) Note 8.43 "Change/Assertion" means either-edge change on any internal IRQs routed to the SIRQ block or assertion of an internal DMA request by a device in SIO10N268. The "assertion" detection logic runs asynchronously to the PCI Clock and regardless of the Serial IRQ mode; i.e., "continuous" or "quiet". The CLKRUN# signal is `1' for at least two consecutive clocks before SIO10N268 asserts (`0') it. Note 8.44 MASTER TARGET Kailua PCI_CLK nCLKRUN PCI CLOCK GENERATOR (Central Resource) Figure 8.9 - CLKRUN# System Implementation Example Rev. 0.5 (03-24-05) Page 144 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet SIRQ_CLKRUN_EN ANY IRQ CHANGE/ DRQ ASSERTION CLKRUN# PCI_CLK 2 CLKS MIN. CLKRUN# DRIVEN BY SIO10N268 SIO10N268 STOPS DRIVING CLKRUN# Figure 8.10 - Clock Start Illustration Note 8.45 The signal "ANY IRQ CHANGE/DRQ ASSERTION" is the same as "CHANGE/ASSERTION" in Table 8.54. The SIO10N268 continually monitors the state of CLKRUN# to maintain the PCI Clock until an active "ANY IRQ CHANGE/DRQ ASSERTION" condition has been transferred to the host in a SER_IRQ/DMA cycle. For example, if "ANY IRQ CHANGE/DRQ ASSERTION" is asserted before CLKRUN# is deasserted (not shown in Figure 8.10), the SIO10N268 must assert CLKRUN# as needed until the SER_IRQ/DMA cycle has completed. Note 8.46 8.16 General Purpose I/O The SIO10N268 provides a set of flexible Input/Output control functions to the system designer through the 33 independently programmable General Purpose I/O pins (GPIO). The GPIO pins can perform basic I/O and many of them can be individually enabled to generate an SMI and a PME. 8.16.1 GPIO Pins The following pins include GPIO functionality as defined in the table below. Table 8.55 - GPIO Pin Functionality PIN 2 20 34 35 36 37 38 39 NAME GP11/DRVDEN1/FDC_PP GP23/LED2/IRQIN2 GP30 /nRI3 GP31/nDCD3 GP32/nRXD3 GP33/nTXD3 GP34/nDSR3 GP35/nRTS3 POWER WELL VCC (Note 8.47) VTR (Note 8.47) VCC (Note 8.47, Note 8.48) VCC (Note 8.47) VCC (Note 8.47) VCC (Note 8.47) VCC (Note 8.47) VCC (Note 8.47) DEFAULT ON VTR POR GPIO Input GPIO Input GPIO Input GPIO Input GPIO Input GPIO Input GPIO Input GPIO Input DEFAULT ON VCC POR Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable GPIO PME/SMI FUNCTION PME/SMI PME/SMI PME PME PME PME PME PME SMSC SIO10N268 Page 145 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet PIN 40 41 42 43 44 45 46 47 48 50 51 53 55 56 60 61 62 90 91 92 93 94 95 96 97 Note 8.47 Note 8.48 NAME GP36/nCTS3 GP37/nDTR3 GP40/nRI4 GP41/nDCD4 GP42/nRXD4 GP43/nTXD4 GP44/nDSR4 GP45/nRTS4 GP46/nCTS4 GP47/nDTR4 GP12/IO_SMI# GP13/IRQIN1/LED1 XA20/GP16 XA19/GP17 GP20/IRRX2/IRQIN3 GP21/IRTX2/WDT GP22/IRMODE/IRRX3/nX CS2 GP50/nRI2 GP51/nDCD2 GP52/RXD2/IRRX GP53/TXD2/IRTX GP54/nDSR2 GP55/nRTS2 GP56/nCTS2 GP57/nDTR2 /MEMEN POWER WELL VCC (Note 8.47) VCC (Note 8.47) VCC (Note 8.48) VCC VCC VCC VCC VCC VCC VCC VCC (Note 8.47) VCC (Note 8.47) VCC (Note 8.47) VCC (Note 8.47) VCC (Note 8.47) VCC (Note 8.47) VCC (Note 8.47) VCC (Note 8.48) VCC VCC VCC VCC VCC VCC VCC DEFAULT ON VTR POR GPIO Input GPIO Input GPIO Input GPIO Input GPIO Input GPIO Input GPIO Input GPIO Input GPIO Input GPIO Input GPIO Input GPIO Input X-Bus Address bit[20] Output X-Bus Address bit[19] Output GPIO Input GPIO Input GPIO Input GPIO Input GPIO Input GPIO Input GPIO Input GPIO Input GPIO Input GPIO Input GPIO Input DEFAULT ON VCC POR Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable GPIO PME/SMI FUNCTION PME PME PME IO_SMI#/ PME/SMI PME/SMI PME/SMI PME/SMI PME PME PME PME - These pins have input buffers into the wakeup logic that are powered by VTR. This pin has an input buffer into the wakeup logic that are powered by VTR to support the nRI function. 8.16.2 Description Each GPIO port has a 1-bit data register. GPIOs are controlled by GPIO control registers located in the Configuration section. The data register for each GPIO port is represented as a bit in one of the 8-bit GPIO DATA Registers, GP1 to GP5. The bits in these registers reflect the value of the associated GPIO pin as follows. Pin is an input: The bit is the value of the GPIO pin. Pin is an output: The value written to the bit goes to the GPIO pin. Latched on read and write. The GPIO data registers are located in the Runtime Register block; see the Runtime Registers section. The GPIO ports with their alternate functions and configuration state register addresses are listed in Table 8.56. Rev. 0.5 (03-24-05) Page 146 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet Table 8.56 - General Purpose I/O Port Assignments PIN NO. /QFP N/A 2 51 53 N/A N/A 55 56 60 61 62 20 N/A N/A N/A N/A 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 50 90 91 92 93 94 95 96 97 Note 8.49 DEFAULT FUNCTION Reserved GPIO GPIO GPIO Reserved Reserved XA20 XA19 GPIO GPIO GPIO GPIO Reserved Reserved Reserved Reserved GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO ALT. FUNC. 1 DRVDEN1 IO_SMI# IRQIN1 ALT. FUNC. 2 FDC_PP nLED1 ALT. FUNC. 3 DATA REGISTER (Note 8.49) GP1 DATA REGISTER BIT NO. 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 REGISTER OFFSET (HEX) 0C GPIO GPIO IRRX2 IRTX2 IRMODE nLED2 IRQIN3 WDT IRRX3 IRQIN2 GP2 nXCS2 0D nRI3 nDCD3 nRXD3 nTXD3 nDSR3 nRTS3 nCTS3 nDTR3 nRI4 nDCD4 nRXD4 nTXD4 nDSR4 nRTS4 nCTS4 nDTR4 nRI5 nDCD5 nRXD5 nTXD5 nDSR5 nRTS5 nCTS5 nDTR5 GP3 0E GP4 0F GP5 0F The GPIO Data Registers are located at the offset shown from the RUNTIME REGISTERS BLOCK address. SMSC SIO10N268 Page 147 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet 8.16.3 GPIO Control Each GPIO port has an 8-bit control register that controls the behavior of the pin. These registers are defined in the Configuration section of this specification. Each GPIO port may be configured as either an input or an output. If the pin is configured as an output, it can be programmed as open-drain or push-pull. Inputs and outputs can be configured as non-inverting or inverting. GPIO Direction Registers determine the port direction, GPIO Polarity Registers determine the signal polarity, and GPIO Output Type Register determines the output driver type select. The GPIO Output Type Registers (CR39, CR40, CR41) apply to certain GPIOs (GP11-GP13, GP16-GP17, GP20, GP21, GP23, and GP50-GP57). The GPIO Direction, Polarity and Output Type Registers control the GPIO pin when the pin is configured for the GPIO function and when the pin is configured for the alternate function for all pins. The basic GPIO configuration options are summarized in Table 8.57. Table 8.57 - GPIO Configuration Summary SELECTED FUNCTION GPIO DIRECTION BIT B0 0 0 1 1 POLARITY BIT B1 0 1 0 1 DESCRIPTION Pin is a non-inverted output. Pin is an inverted output. Pin is a non-inverted input. Pin is an inverted input. 8.16.4 GPIO Operation The operation of the GPIO ports is illustrated in Figure 8.11. Rev. 0.5 (03-24-05) Page 148 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet GPIO Configuration Register bit-1 (Polarity) GPIO Configuration Register bit-0 (Input/Output) SD-bit GPx_nIOW D-TYPE D Q Transparent 0 1 Q GPx_nIOR D GPIO PIN GPIO Data Register Bit-n Figure 8.11 - GPIO Function NOTE: Figure 8.11 is for illustration purposes only and in not intended to suggest specific implementation details. When a GPIO port is programmed as an input, reading it through the GPIO data register latches either the inverted or non-inverted logic value present at the GPIO pin. Writing to a GPIO port that is programmed as an input has no effect (Table 8.58). When a GPIO port is programmed as an output, the logic value or the inverted logic value that has been written into the GPIO data register is output to the GPIO pin. Reading from a GPIO port that is programmed as an output returns the last value written to the data register (Table 8.58). Table 8.58 - GPIO Read/Write Behavior HOST OPERATION READ WRITE GPIO INPUT PORT GPIO OUTPUT PORT LATCHED VALUE OF GPIO PIN LAST WRITE TO GPIO DATA REGISTER NO EFFECT BIT PLACED IN GPIO DATA REGISTER The SIO10N268 provides 20 GPIOs that can directly generate a PME. See the table in the next section. The GPIO Polarity Registers in the Configuration section select the edge on these GPIO pins that will set the associated status bit in the PME_STS1 - PME_STS4 registers. The default is the low-to-high edge. If the corresponding enable bit in the PME_EN1 - PME_EN4 registers and the PME_EN bit in the PME_EN register is set, a PME will be generated. These registers are located in the Runtime Registers Block, which is located at the address contained in the configuration registers CR30. The PME status bits for the GPIOs are cleared on a write of `1'. In addition, the SIO10N268 provides 6 GPIOs that can directly generate an SMI. See the table in the next section. SMSC SIO10N268 Page 149 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet 8.16.5 GPIO, PME and SMI Functionality The following GPIOs are dedicated wakeup GPIOs with a status and enable bit in the PME status and enable registers: GP11-GP13 GP16-GP17 GP20-GP23 GP30-GP37 GP40 GP50 This following is the list of PME status and enable registers for their corresponding GPIOs: PME_STS1 and PME_EN1 for GP11-GP13 and GP16-GP17 PME_STS2 and PME_EN2 for GP20-GP23 and GP50 PME_STS3 and PME_EN3 for GP30-GP37 PME_STS4 and PME_EN4 for GP30 and GP40 The following GPIOs can directly generate an SMI and have a status and enable bit in the SMI status and enable registers. GP11-GP13 GP16-GP17 GP23 The following SMI status and enable registers for these GPIOs: SMI_STS1 and SMI_EN1 for GP11-GP13 and GP16-GP17 SMI_STS2 and SMI_EN2 for GP23 Table 8.59 - PME and SMI Functionality for each GPIO GPIO GP11 GP12 GP13 GP16-GP17 GP20-GP22 GP23 GP30-GP37 GP40 GP41-GP47 GP50 GP51-GP57 PME Yes Yes Yes Yes Yes Yes Yes Yes No Yes No SMI Yes Yes/IO_SMI# Yes Yes No Yes No No No No No OUTPUT BUFFER POWER VCC VCC VCC VCC VCC VTR VCC VCC VCC VCC VCC NOTES Note 8.50 Note 8.51 Note 8.51 Note 8.50 Since GP12 can be used to generate an SMI and as the IO_SMI# output, do not enable GP12 to generate an SMI (by setting bit 2 of the SMI Enable Register 1) if the IO_SMI# function is selected on the GP12 pin. Use GP12 to generate an SMI event only if the SMI output is enabled on the Serial IRQ stream. Rev. 0.5 (03-24-05) Page 150 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet Note 8.51 GP41-GP47 and GP51-GP57 should not be connected to any VTR powered external circuitry. These pins are not used for wakeup. 8.17 System Management Interrupt (SMI) The SIO10N268 implements a "group" IO_SMI# output pin. The System Management Interrupt is a nonmaskable interrupt with the highest priority level used for OS transparent power management. The nSMI group interrupt output consists of the enabled interrupts from Super I/O Device Interrupts (Parallel Port, Serial Ports 1, 2, 3, and 4, and FDC) and many of the GPIOs pins. The GP12/IO_SMI# pin, when selected for the IO_SMI# function, can be programmed to be active high or active low via bit[2] in the GPIO Polarity Register 1 (CR32). The IO_SMI# pin function defaults to active low. The output buffer type of the pin can be programmed to be open-drain or push-pull via GPIO Output Type Register 1 (CR39). The interrupts are enabled onto the group nSMI output via the SMI Enable Registers 1, 2, and 3. The nSMI output is then enabled onto the IO_SMI# output pin via bit[7] in the SMI Enable Register 2. The SMI output can also be enabled onto the serial IRQ stream (IRQ2) via Bit[6] in the SMI Enable Register 2. 8.17.1 SMI Registers There are six SMI Registers located in the Runtime Register block. They are SMI_EN1, SMI_EN2, SMI_EN3, SMI_STS1, SMI_STS2, and SMI_STS3. The SMI event bits for the GPIOs events are located in the SMI status and Enable registers 1 and 2. The polarity of the edge used to set the status bit and generate an SMI is controlled by the GPIO Polarity Registers located in the Configuration section. For non-inverted polarity (default) the status bit is set on the low-to-high edge. Status bits for the GPIOs are cleared on a write of `1'. The SMI logic for the GPIO events is implemented such that the output of the status bit for each event is combined with the corresponding enable bit in order to generate an SMI. The SMI event bits for the super I/O devices are located in the SMI status and enable registers 2 and 3. All of these status bits are cleared at the source; these status bits are not cleared by a write of `1'. The SMI logic for these events is implemented such that each event is directly combined with the corresponding enable bit in order to generate an SMI. See Chapter 9 Runtime Registers for the definition of the SMI status and enable registers. 8.18 PME Support The SIO10N268 offers support for Power Management Events (PMEs), also referred to as System Control Interrupt (SCI) events in an ACPI system. A power management event is indicated to the chipset via the assertion of the IO_PME# signal. In the SIO10N268, the IO_PME# is asserted by active transitions on the ring indicator inputs nRI1, nRI2, nRI3, and nRI4, Watchdog Timer Event (WDT), and programmable edges on GPIO pins. The nIO_PME pin can be programmed to be active high or active low via bit 5 in the GPIO Polarity Register 2 (CR34). The nIO_PME pin function defaults to active low, open-drain output. The output buffer type of the pin can be programmed to be open-drain or push-pull via bit 7 in the GPIO Output Type Register 2 (CR40). This pin is powered by VTR. See the Configuration section for description on these registers. PME functionality is controlled by the PME status and enable registers in the runtime registers block, which is located at the address programmed in register 0x30 in the Configuration section. The PME Enable bit, PME_EN, globally controls PME Wake-up events. When PME_EN is inactive, the IO_PME# signal can not be asserted. When PME_EN is asserted, any wake source whose individual PME Wake Enable register bit is asserted can cause IO_PME# to become asserted. SMSC SIO10N268 Page 151 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet The PME Status register indicates that an enabled wake source has occurred and if the PME_EN bit is set, asserted the IO_PME# signal. The PME Status bit is asserted by active transitions of PME wake sources. PME_STS will become asserted independent of the state of the global PME enable, PME_EN. The following pertains to the PME status bits for each event: The output of the status bit for each event is combined with the corresponding enable bit to set the PME status bit. The status bit for any pending events must be cleared in order to clear the PME_STS bit. Status bits are cleared on a write of `1'. For the GPIO events, the polarity of the edge used to set the status bit and generate a PME is controlled by the GPIO Polarity Registers in the Configuration section. For non-inverted polarity (default) the status bit is set on the low-to-high edge. Status bits are cleared on a write of `1'. In the SIO10N268 the IO_PME# pin can be programmed to be an open drain, active low, driver. The SIO10N268 IO_PME# pin is fully isolated from other external devices that might pull the IO_PME# signal low; i.e., the IO_PME# signal is capable of being driven high externally by another active device or pullup even when the SIO10N268 VCC is grounded, providing VTR power is active. 8.18.1 PME Registers There are eight PME Registers located in the Runtime Register block. They are PME_EN1, PME_EN2, PME_EN3, PME_EN4, PME_STS1, PME_STS2, PME_STS3, and PME_STS4. These registers are located in system I/O space at an offset from Runtime Registers Block, the address programmed at register 0x30 in the Configuration section. The following registers are for GPIO PME events: PME Wake Status 1 (PME_STS1), PME Wake Enable 1 (PME_EN1) PME Wake Status 2 (PME_STS2), PME Wake Enable 2 (PME_EN2) PME Wake Status 3 (PME_STS3), PME Wake Enable 3 (PME_EN3) PME Wake Status 4 (PME_STS4), PME Wake Enable 4 (PME_EN4) See PME register description in Chapter 9 Runtime Registers. Rev. 0.5 (03-24-05) Page 152 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet Chapter 9 9.1 Runtime Registers Runtime Registers Block Summary The runtime registers are located at the address programmed in the Runtime Register Block Base Address configuration register located in CR30. The part performs 16-bit address qualification on the Runtime Register Base Address (bits[11:0] are decoded and bits[15:12] must be zero). The runtime register block may be located within the range 0x0100-0x0FFF on 16-byte boundaries. Decodes are disabled if the Runtime Register Base Address is located below 0x100. These registers are powered by VTR. Table 9.1 - Runtime Register Block Summary REGISTER OFFSET (hex) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B TYPE R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note 9.2 R/W R/W R R/W R/W R/W R/W Hard RESET (Note 9.3) Note 9.1 0x00 0x00 0x00 0x00 - VCC POR Note 9.1 0x00 0x00 0x00 0x00 - VTR POR 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 Note 9.1 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 REGISTER PME_STS PME_EN PME_STS1 PME_STS2 PME_STS3 PME_EN1 PME_EN2 PME_EN3 SMI_STS1 SMI_STS2 SMI_EN1 SMI_EN2 GP1 GP2 GP3 GP4 GP5 WDT_TIME_OUT WDT_VAL WDT_CFG WDT_CTRL LED1 LED2 Reserved SMI_STS3 SMI_EN3 PME_STS4 PME_EN4 NOTE: Reserved bits return 0 on read. SMSC SIO10N268 Page 153 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet Note 9.1 The parallel port interrupt defaults to 1 when the parallel port power bit is cleared. When the parallel port is activated, PINT follows the nACK input. This register contains some bits that are read or write only. Hard Reset = PCI_RESET# OR RESET_DRV. Note 9.2 Note 9.3 9.2 Runtime Registers Block Description Table 9.2 - Runtime Registers Block Description NAME/DEFAULT PME_STS Default = 0x00 on VTR POR REGISTER OFFSET 00 (R/W) DESCRIPTION Bit[0] PME_Status = 0 (default) = 1 Set when SIO10N268 would normally assert the IO_PME# signal, independent of the state of the PME_En bit. Bit[7:1] Reserved PME_Status is not affected by Vcc POR, SOFT RESET or HARD RESET. Writing a "1" to PME_Status will clear it and cause the SIO10N268 to stop asserting IO_PME#, in enabled. Writing a "0" to PME_Status has no effect. Bit[0] PME_En = 0 IO_PME# signal assertion is disabled (default) = 1 Enables SIO10N268 to assert IO_PME# signal Bit[7:1] Reserved PME_En is not affected by Vcc POR, SOFT RESET or HARD RESET PME Wake Status Register 1 This register indicates the state of the individual PME wake sources, independent of the individual source enables or the PME_En bit. If the wake source has asserted a wake event, the associated PME Wake Status bit will be a "1". Bit[0] Reserved Bit[1] GP11 Bit[2] GP12 Bit[3] GP13 Bit[4] Reserved Bit[5] Reserved Bit[6] GP16 Bit[7] GP17 The PME Wake Status register is not affected by Vcc POR, SOFT RESET or HARD RESET. Writing a "1" to Bit[7:0] will clear it. Writing a "0" to any bit in PME Wake Status Register has no effect. Note: Status bits are set by an event on the pin regardless of the Alternate Function selected. PME_EN Default = 0x00 on VTR POR 01 (R/W) PME_STS1 Default = 0x00 on VTR POR 02 (R/W) Rev. 0.5 (03-24-05) Page 154 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet NAME/DEFAULT PME_STS2 Default = 0x00 on VTR POR REGISTER OFFSET 03 (R/W) DESCRIPTION PME Wake Status Register 2 This register indicates the state of the individual PME wake sources, independent of the individual source enables or the PME_En bit. If the wake source has asserted a wake event, the associated PME Wake Status bit will be a "1". Bit[0] nRI1 Bit[1] nRI2/GP50 Bit[2] GP20 Bit[3] GP21 Bit[4] GP22 Bit[5] GP23 Bit[6] Reserved Bit[7] WDT Writing a "1" to Bit[7:0] will clear it. Writing a "0" to any bit in PME Wake Status Register has no effect. Note: Status bits are set by an event on the pin regardless of the Alternate Function selected. PME Wake Status Register 3 This register indicates the state of the individual PME wake sources, independent of the individual source enables or the PME_En bit. If the wake source has asserted a wake event, the associated PME Wake Status bit will be a "1". Bit[0] GP30/nRI3 Bit[1] GP31 Bit[2] GP32 Bit[3] GP33 Bit[4] GP34 Bit[5] GP35 Bit[6] GP36 Bit[7] GP37 The PME Wake Status register is not affected by Vcc POR, SOFT RESET or HARD RESET. Writing a "1" to Bit[7:0] will clear it. Writing a "0" to any bit in PME Wake Status Register has no effect. Note: Status bits are set by an event on the pin regardless of the Alternate Function selected. PME_STS3 Default = 0x00 on VTR POR 04 (R/W) SMSC SIO10N268 Page 155 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet NAME/DEFAULT PME_EN1 Default = 0x00 on VTR POR REGISTER OFFSET 05 (R/W) DESCRIPTION PME Wake Enable Register 1 This register is used to enable individual SIO10N268 PME wake sources onto the IO_PME# wake bus. When the PME Wake Enable register bit for a wake source is active ("1"), if the source asserts a wake event so that the associated status bit is "1" and the PME_En bit is "1", the source will assert the IO_PME# signal. When the PME Wake Enable register bit for a wake source is inactive ("0"), the PME Wake Status register will indicate the state of the wake source but will not assert the IO_PME# signal. Bit[0] Reserved Bit[1] GP11 Bit[2] GP12 Bit[3] GP13 Bit[4] Reserved Bit[5] Reserved Bit[6] GP16 Bit[7] GP17 The PME Wake Enable register is not affected by Vcc POR, SOFT RESET or HARD RESET. PME Wake Enable Register 2 This register is used to enable individual SIO10N268 PME wake sources onto the IO_PME# wake bus. When the PME Wake Enable register bit for a wake source is active ("1"), if the source asserts a wake event so that the associated status bit is "1" and the PME_En bit is "1", the source will assert the IO_PME# signal. When the PME Wake Enable register bit for a wake source is inactive ("0"), the PME Wake Status register will indicate the state of the wake source but will not assert the IO_PME# signal. Bit[0] nRI1 Bit[1] nRI2/GP50 Bit[2] GP20 Bit[3] GP21 Bit[4] GP22 Bit[5] GP23 Bit[6] Reserved Bit[7] WDT PME_EN2 Default = 0x00 on VTR POR 06 (R/W) Rev. 0.5 (03-24-05) Page 156 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet NAME/DEFAULT PME_EN3 Default = 0x00 on VTR POR REGISTER OFFSET 07 (R/W) DESCRIPTION PME Wake Enable Register 3 This register is used to enable individual SIO10N268 PME wake sources onto the IO_PME# wake bus. When the PME Wake Enable register bit for a wake source is active ("1"), if the source asserts a wake event so that the associated status bit is "1" and the PME_En bit is "1", the source will assert the IO_PME# signal. When the PME Wake Enable register bit for a wake source is inactive ("0"), the PME Wake Status register will indicate the state of the wake source but will not assert the IO_PME# signal. Bit[0] GP30/nRI3 Bit[1] GP31 Bit[2] GP32 Bit[3] GP33 Bit[4] GP34 Bit[5] GP35 Bit[6] GP36 Bit[7] GP37 The PME Wake Enable register is not affected by Vcc POR, SOFT RESET or HARD RESET. SMI Status Register 1 This register is used to read the status of the SMI inputs. The following bits are cleared on a write of `1'. Bit[0] Reserved Bit[1] GP11 Bit[2] GP12 Bit[3] GP13 Bit[4] Reserved Bit[5] Reserved Bit[6] GP16 Bit[7] GP17 SMI Status Register 2 This register is used to read the status of the SMI inputs. The bits[3:0] must be cleared at their source. Bits[5:4] are cleared on a write of `1'. Bit[0] PINT. The parallel port interrupt defaults to `1' when the parallel port activate bit is cleared. When the parallel port is activated, PINT follows the nACK input. Bit[1] U2INT Bit[2] U1INT Bit[3] FINT Bit[4] GP23 Bit[7:5] Reserved SMI_STS1 Default = 0x00 on VTR POR 08 (R/W) SMI_STS2 Default = 0x01 on VTR POR Bit 0 is set to `1' on VCC POR, VTR POR and HARD RESET 09 (R/W) SMSC SIO10N268 Page 157 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet NAME/DEFAULT SMI_EN1 Default = 0x00 on VTR POR REGISTER OFFSET 0A (R/W) DESCRIPTION SMI Enable Register 1 This register is used to enable the different interrupt sources onto the internal group nSMI signal. 1=Enable 0=Disable Bit[0] Reserved Bit[1] GP11 Bit[2] GP12 Bit[3] GP13 Bit[4] Reserved Bit[5] Reserved Bit[6] GP16 Bit[7] GP17 SMI Enable Register 2 This register is used to enable the different interrupt sources onto the internal group nSMI signal, and the internal group nSMI signal onto the IO_SMI# GPI/O pin or the serial IRQ stream on IRQ2. 1=Enable 0=Disable Bit[0] EN_PINT Bit[1] EN_U2INT Bit[2] EN_U1INT Bit[3] EN_FINT Bit[4] GP23 Bit[5] Reserved Bit[6] EN_SMI_S (Enable group nSMI signal onto serial IRQ2) Bit[7] EN_SMI (Enable group nSMI signal onto IO_SMI# pin) General Purpose I/O Data Register 1 Bit[0]Reserved Bit[1]GP11 Bit[2]GP12 Bit[3]GP13 Bit[4]Reserved Bit[5]Reserved Bit[6]GP16 Bit[7]GP17 General Purpose I/O Data Register 2 Bit[0]GP20 Bit[1]GP21 Bit[2]GP22 Bit[3]GP23 Bit[7:4]Reserved SMI_EN2 Default = 0x00 on VTR POR 0B (R/W) GP1 Default = 0x00 on VTR POR 0C R/W GP2 Default = 0x00 on VTR POR 0D R/W Rev. 0.5 (03-24-05) Page 158 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet NAME/DEFAULT GP3 Default = 0x00 on VTR POR REGISTER OFFSET 0E R/W DESCRIPTION General Purpose I/O Data Register 3 Bit[0]GP30 Bit[1]GP31 Bit[2]GP32 Bit[3]GP33 Bit[4]GP34 Bit[5]GP35 Bit[6]GP36 Bit[7]GP37 General Purpose I/O Data Register 4 Bit[0]GP40 Bit[1]GP41 Bit[2]GP42 Bit[3]GP43 Bit[4]GP44 Bit[5]GP45 Bit[6]GP46 Bit[7]GP47 General Purpose I/O Data Register 5 Bit[0]GP50 Bit[1]GP51 Bit[2]GP52 Bit[3]GP53 Bit[4]GP54 Bit[5]GP55 Bit[6]GP56 Bit[7]GP57 Watchdog Timeout Bits[6:0] Reserved Bit[7] WDT Time-out Value Units Select = 0 Minutes (default) = 1 Seconds Watchdog Timer Time-out Value Binary coded, units = minutes (default) or seconds, selectable via Bit[7] of WDT_TIME_OUT register (0x52). 0x00 Time out disabled 0x01 Time-out = 1 minute (second) ......... 0xFF Time-out = 255 minutes (seconds) GP4 Default = 0x00 on VTR POR 0F R/W GP5 Default = 0x00 on VTR POR 10 R/W WDT_TIME_OU T Default = 0x00 on VCC POR, VTR POR, and Hard Reset WDT_VAL Default = 0x00 on VCC POR, VTR POR, and Hard Reset 11 (R/W) 12 (R/W) SMSC SIO10N268 Page 159 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet NAME/DEFAULT WDT_CFG Default = 0x00 on VCC POR, VTR POR, and Hard Reset REGISTER OFFSET 13 (R/W) DESCRIPTION Watchdog timer Configuration Bit[3:0] Reserved Bits[7:4] WDT Interrupt Mapping 1111 = IRQ15 ......... 0011 = IRQ3 0010 = Invalid 0001 = IRQ1 0000 = Disable Watchdog timer Control Bit[0] Watchdog Status Bit, R/W (Note) =1 WD timeout occurred =0 WD timer counting Bit[1] Reserved Bit[2] Force Timeout, W =1 Forces WD timeout event; this bit is self-clearing Bit[3] Reserved Bit[7:4] Reserved. Set to 0 Note: If WDT is disabled (i.e., WDT_VAL register is 00h) bit[0] is forced to `0' Bit[1:0] LED1 Control 00=off 01=Blink at 1Hz rate with a 50% duty cycle (0.5 sec on, 0.5 sec off) 10=Blink at 1/2 HZ rate with a 25% duty cycle (0.5 sec on, 1.5 sec off) 11=on Bits[7:2] Reserved Bit[1:0] LED2 Control 00=off 01=Blink at 1Hz rate with a 50% duty cycle (0.5 sec on, 0.5 sec off) 10=Blink at 1/2 Hz rate with a 25% duty cycle (0.5 sec on, 1.5 sec off) 11=on Bits[7:2] Reserved Reads return 0. SMI Status Register 3 This register is used to read the status of the SMI inputs. Bit[0] is cleared on a write of `1'. Bit[0] WDT Bit[1] U3INT Bit[2] U4INT Bit[7:3] Reserved WDT_CTRL Default = 0x00 on VCC POR, VTR POR, and Hard Reset 14 (R/W) Bit[2] is Write-Only LED1 Default = 0x00 on VTR POR 15 (R/W) LED2 Default = 0x00 on VTR POR 16 (R/W) Reserved SMI_STS3 Default = 0x00 on VTR POR 17 18 (R/W) Rev. 0.5 (03-24-05) Page 160 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet NAME/DEFAULT SMI_EN3 Default = 0x00 on VTR POR REGISTER OFFSET 19 (R/W) DESCRIPTION SMI Enable Register 3 This register is used to enable the different interrupt sources onto the internal group nSMI signal. 1=Enable 0=Disable Bit[0] EN_WDT Bit[1] EN_U3INT Bit[2] EN_U4INT Bit[7:3] Reserved PME Wake Status Register 4 This register indicates the state of the individual PME wake sources, independent of the individual source enables or the PME_En bit. If the wake source has asserted a wake event, the associated PME Wake Status bit will be a "1". Bit[0] nRI3/GP30 Bit[1] nRI4/GP40 Bit[2] Reserved Bit[3] Reserved Bit[4] Reserved Bit[5] Reserved Bit[6] Reserved Bit[7] Reserved Writing a "1" to Bit[1:0] will clear it. Writing a "0" to any bit in PME Wake Status Register has no effect. Note: Status bits are set by an event on the pin regardless of the Alternate Function selected. PME Wake Enable Register 4 This register is used to enable individual SIO10N268 PME wake sources onto the IO_PME# wake bus. When the PME Wake Enable register bit for a wake source is active ("1"), if the source asserts a wake event so that the associated status bit is "1" and the PME_En bit is "1", the source will assert the IO_PME# signal. When the PME Wake Enable register bit for a wake source is inactive ("0"), the PME Wake Status register will indicate the state of the wake source but will not assert the IO_PME# signal. Bit[0] nRI3/GP30 Bit[1] nRI4/GP40 Bit[2] Reserved Bit[3] Reserved Bit[4] Reserved Bit[5] Reserved Bit[6] Reserved Bit[7] Reserved PME_STS4 Default = 0x00 on VTR POR 1A (R/W) PME_EN4 Default = 0x00 on VTR POR 1B (R/W) NOTE: Reserved bits return 0 on read. SMSC SIO10N268 Page 161 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet Rev. 0.5 (03-24-05) Page 162 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet Chapter 10 Configuration The configuration of the SIO10N268 is programmed through hardware selectable Configuration Access Ports that appear when the chip is placed into the configuration state. The SIO10N268 logical device blocks, if enabled, will operate normally in the configuration state. 10.1 Configuration Access Ports The Configuration Access Ports are the CONFIG PORT, the INDEX PORT, and the DATA PORT (Table 10.1). The base address of these registers is controlled by the nRTS1/SYSOPT pin and by the Configuration Port Base Address registers CR12 and CR13. To determine the configuration base address at power-up, the state of the nRTS1/SYSOPT pin is latched by the trailing edge of a hardware reset (deasserting edge of PCI_RESET#). If the latched state is a 0, the base address of the Configuration Access Ports is located at address 0x02E; if the latched state is a 1, the base address is located at address 0x04E. The base address is relocatable via CR12 and CR13. Table 10.1 - Configuration Access Ports PORT NAME CONFIG PORT INDEX PORT DATA PORT SYSOPT = 0 0x02E 0x02E SYSOPT = 1 0x04E 0x04E TYPE WRITE READ/WRITE (Note 10.1, Note 10.2) READ/WRITE (Note 10.1) INDEX PORT + 1 Note 10.1 Note 10.2 The INDEX and DATA ports are active only when the SIO10N268 is in the configuration state. The INDEX PORT is only readable in the configuration state. 10.2 Configuration State The configuration registers are used to select programmable chip options. The SIO10N268 operates in two possible states: the run state and the configuration state. After power up by default the chip is in the run state. To program the configuration registers, the configuration state must be explicitly enabled. Programming the configuration registers typically follows this sequence: 1) 2) 3) Enter the Configuration State, Program the Configuration Register(s), Exit the Configuration State. 10.2.1 Entering the Configuration State To enter the configuration state write the Configuration Access Key to the CONFIG PORT. The Configuration Access Key is one byte of 55H data. The SIO10N268 will automatically activate the Configuration Access Ports following this procedure. 10.2.2 Configuration Register Programming The SIO10N268 contains configuration registers CR00-CR54. After the SIO10N268 enters the configuration state, configuration registers can be programmed by first writing the register index number (00 - 54H) to the Configuration Select Register (CSR) through the INDEX PORT and then writing or SMSC SIO10N268 Page 163 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet reading the configuration register contents through the DATA PORT. remains enabled until the configuration state is explicitly exited. Configuration register access 10.2.3 Exiting the Configuration State To exit the configuration state, write one byte of AAH data to the CONFIG PORT. The SIO10N268 will automatically deactivate the Configuration Access Ports following this procedure, at which point configuration register access cannot occur until the configuration state is explicitly re-enabled. 10.2.3.1 Programming Example The following is a configuration register programming example written in Intel 8086 assembly language. ;----------------------------. ; ENTER CONFIGURATION STATE | ;----------------------------' MOV DX,02EH ;SYSOPT = 0 MOV AX,055H OUT DX,AL ;----------------------------. ; CONFIGURE REGISTER CR0-CRx | ;----------------------------' MOV DX,02EH MOV AL,00H OUT DX,AL ;Point to CR0 MOV DX,02FH MOV AL,3FH OUT DX,AL ;Update CR0 ; MOV DX,02EH MOV AL,01H OUT DX,AL ;Point to CR1 MOV DX,02FH MOV AL,9FH OUT DX,AL ;Update CR1 ; ; Repeat for all CRx registers ; ;-----------------------------. ; EXIT CONFIGURATION STATE | ;-----------------------------' MOV DX,02EH MOV AX,AAH OUT DX,AL Rev. 0.5 (03-24-05) Page 164 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet 10.2.3.2 Configuration Select Register (CSR) The Configuration Select Register can only be accessed when the SIO10N268 is in the configuration state. The CSR is located at the INDEX PORT address and must be initialized with configuration register index before the register can be accessed using the DATA PORT. 10.3 Configuration Registers Summary The configuration registers are set to their default values at power up (Table 10.2) and are RESET as indicated in Table 10.2 and the register descriptions that follow. Table 10.2 - Configuration Registers Summary REGISTER INDEX CR00 CR01 CR02 CR03 CR04 CR05 CR06 CR07 CR08 CR09 CR0A CR0B CR0C CR0D CR0E CR0F CR10 CR11 CR12 CR13 CR14 CR15 CR16 CR17 CR18 CR19 CR1A CR1B TYPE R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R R R/W R/W R/W R/W R/W R R R R/W R/W R R R/W Hard RESET VCC POR (Note 10.4) Bit[3] = 0 0x20 bit[7]=1 0x98 Bit[2]=0 0x00 0x00 0x70 0x00 0x00 0xFF bit[7:2]=0 0x00 0x00 0x00 bit[7:6]=0 0x00 0x00 0x02 0x02 0x5B Revision 0x00 0x00 0x00 SYSOPT=0:0x2E SYSOPT=1:0x4E SYSOPT=0:0x00 SYSOPT=1:0x00 0x03 0x03 bit[7:6]=0 0x00 0x00 VTR POR - REGISTER FDC Power/Valid Config Cycle PP Power/Mode/CR Lock UART Power FDC Miscellaneous PP and UART Miscellaneous FDC Setup Drive Type ID Auto Power Mgt/Boot Drive Select Reserved Test 4 ECP FIFO Threshold/IR MUX Drive Rate UART Mode Device ID Revision ID Test 1 Test 2 Test 3 Configuration Base Address 0 Configuration Base Address 1 DSR Shadow UART1 FCR Shadow UART2 FCR Shadow Force FDD Status Change UART 3,4 Miscellaneous UART3 FCR Shadow UART4 FCR Shadow UART3 Base Address SMSC SIO10N268 Page 165 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet REGISTER INDEX CR1C CR1D CR1E CR1F CR20 CR21 CR22 CR23 CR24 CR25 CR26 CR27 CR28 CR29 CR2A CR2B CR2C CR2D CR2E CR2F CR30 CR31 CR32 CR33 CR34 CR35 CR36 CR37 CR38 CR39 CR3A CR3B CR3C CR3D CR3E CR3F CR40 CR41 CR42 CR43 CR44 CR45 TYPE R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R/W R/W R/W R/W R/W R/W Hard RESET (Note 10.4) 0x00 bit[7:4]= 0101 VCC POR 0x00 0x00 0x00 0x3C 0x00 0x00 0x00 0x00 0x00 0xFF 0x00 0x00 0x80 0x00 0x00 0x0F 0x03 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 bit[7:4]= 0101 VTR POR 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x80 0x00 0x00 0x00 0x00 0x50 REGISTER UART4 Base Address UART 3,4 IRQ Select Clock/AEN Control Register Drive Type FDC Base Address FDC on PP/EPP Timeout Select ECP Software Select Parallel Port Base Address UART1 Base Address UART2 Base Address FDC and PP DMA Select FDC and PP IRQ Select UART IRQ Select IRQIN1/HPMODE/SIRQ_CLKRUN_E n IRQIN2/IRQIN3 SCE (FIR) Base Address SCE (FIR) DMA Select IR Half Duplex Timeout Software Select A Software Select B Runtime Register Block Address GPIO Direction Register 1 GPIO Polarity Register 1 GPIO Direction Register 2 GPIO Polarity Register 2 GPIO Direction Register 3 GPIO Polarity Register 3 GPIO Direction Register 4 GPIO Polarity Register 4 GPIO Output Type Register 1 Test 5 Reserved Reserved Reserved Reserved Reserved GPIO/MISC Output Type Register 2 GPIO Output Type Register 5 GPIO Direction Register 5 GPIO Polarity Register 5 GPIO Alternate Function Select Register 1 GPIO Alternate Function Select Register 2 Rev. 0.5 (03-24-05) Page 166 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet REGISTER INDEX CR46 CR47 CR48 CR49 CR4A CR4B CR4C CR4D CR4E TYPE R/W R/W R/W R/W R/W R/W R/W R/W R/W (Note 10.3) R/W (Note 10.3) R/W (Note 10.3) R/W (Note 10.3) R/W R/W (Note 10.3) R/W Hard RESET (Note 10.4) 0x00 VCC POR 0x00 0x00 VTR POR 0x00 0x00 0x00 0x00 0x00 0x00 0x00 - REGISTER GPIO Alternate Function Select Register 3 Reserved GPIO Alternate Function Select Register 5 GPIO Alternate Function Select Register 6 GPIO Alternate Function Select Register 7 GPIO Alternate Function Select Register 8 GPIO Alternate Function Select Register 9 GPIO Alternate Function Select Register 10 X-Bus Base I/O Address for Chip Select 1 - High Byte X-Bus Base I/O Address for Chip Select 1 - Low Byte X-Bus Base I/O Address for Chip Select 2 - High Byte X-Bus Base I/O Address for Chip Select 2 - Low Byte X-Bus I/O Select X-Bus Chip Select 0 CR4F 0x01 0x01 - CR50 0x00 0x00 - CR51 0x01 0x01 - CR52 CR53 0x00 0x8C 0x00 0x8C - CR54 0XX00000b (Note 10.5) 0XX00000b (Note 10.5) - FWH ID SELECT NOTE: Note 10.3 Note 10.4 Note 10.5 Reserved registers are read-only, reads return 0. These registers are read-only if the write protect bit is set. Hard Reset = PCI_RESET# OR RESET_DRV X=Strap Options 10.4 Configuration Registers Description 10.4.1 CR00 CR00 can only be accessed in the configuration state and after the CSR has been initialized to 00H. SMSC SIO10N268 Page 167 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet Table 10.3 - CR00 FDC POWER/VALID CONFIGURATION CYCLE DEFAULT: 0x20 on VCC POR TYPE: R/W Bit[3] = 0 on a Hard Reset BIT NAME DESCRIPTION Reserved Read Only. A read returns 0 FDC Power A high level on this bit, supplies power to the FDC. A low level on this bit puts the FDC in low power mode (default). (Note 10.6) Reserved Read only. A read returns bit 5 as a 1 and bits 4 and 6 as a 0. Valid A high level on this software controlled bit can be used to indicate that a valid configuration cycle has occurred. The control software must take care to set this bit at the appropriate times. Set to zero after power up. This bit has no effect on any other hardware in the chip. BIT NO. 0-2 3 4,5,6 7 Note 10.6 Power Down bits disable the respective logical device and associated pins, however the power down bit does not disable the selected address range for the logical device. To disable the host address registers the logical device's base address must be set below 100h. Devices that are powered down but still reside at a valid I/O base address will participate in Plug-and-Play range checking. 10.4.2 CR01 CR01 can only be accessed in the configuration state and after the CSR has been initialized to 01H. Table 10.4 - CR01 PP POWER/MODE/CR LOCK DEFAULT: 0x98 on VCC POR; Bit[7] = 1 and Bit[2]=0 on HARD RESET DESCRIPTION Read Only. A read returns "0". A high level on this bit, supplies power to the Parallel Port. A low level on this bit puts the Parallel Port in low power mode (Default). Parallel Port Mode. A high level on this bit, sets the Parallel Port for Printer Mode (Default). A low level on this bit enables the Extended Parallel port modes. Refer to Bits 0 and 1 of CR4 Read Only. A read returns "1". Read Only. A read returns "0". A high level on this bit enables the reading and writing of CR00 - CR39 (Default). A low level on this bit disables the reading and writing of CR00 - CR39. Note: once the Lock CRx bit is set to "0", this bit can only be set to "1" by a hard reset or power-up reset. TYPE: R/W BIT NO. 0,1 2 3 BIT NAME Reserved Parallel Port Power (Note 10.7, Note 10.8) Parallel Port Mode Reserved Reserved Lock CRx 4 5,6 7 Note 10.7 Power Down bits disable the respective logical device and associated pins, however the power down bit does not disable the selected address range for the logical device. To disable the host address registers the logical device's base address must be set below 100h. Devices that are powered down but still reside at a valid I/O base address will participate in Plug-and-Play range checking. On a VCC POR and a Hard Reset the Parallel Port defaults to powered off. When the Parallel Port Power bit is cleared the parallel port interrupt (PINT) located in the SMI_STS2 register at offset 0x09 is set to `1'. Note 10.8 Rev. 0.5 (03-24-05) Page 168 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet 10.4.3 CR02 CR02 can only be accessed in the configuration state and after the CSR has been initialized to 02H. Table 10.5 - CR02 UART Power TYPE: R/W BIT NO. 0 1 DEFAULT: 0x00 on VCC POR and Hard Reset DESCRIPTION Read Only. A read returns "0". A high level on this bit, allows normal operation of the Primary Serial Port. A low level on this bit places the Primary Serial Port into Power Down Mode (Default). A high level on this bit, allows normal operation of the Primary Serial Port. A low level on this bit places the Primary Serial Port into Power Down Mode (Default). A high level on this bit, allows normal operation of the Primary Serial Port. A low level on this bit places the Primary Serial Port into Power Down Mode (Default). Read Only. A read returns "0". A high level on this bit, allows normal operation of the Secondary Serial Port, including the SCE/FIR block. A low level on this bit places the Secondary Serial Port including the SCE/FIR block into Power Down Mode (Default). BIT NAME Reserved UART3 Power (Note 10.9, Note 10.10) 2 UART4 Power (Note 10.9, Note 10.10) 3 UART1 Power (Note 10.9) 4-6 7 Reserved UART2 Power (Note 10.9, Note 10.10) Note 10.9 Power Down bits disable the respective logical device and associated pins, however the power down bit does not disable the selected address range for the logical device. To disable the host address registers the logical device's base address must be set below 100h. Devices that are powered down but still reside at a valid I/O base address will participate in Plug-and-Play range checking. Note 10.10 The UART pins must be configured for their alternate function prior to enabling the UART power bits. In addition, the IRCC should be configured for the appropriate mode of operation before the UART2 Power bit is set. This is to ensure the state of the transmit and receive pins are in their inactive state for the external device attached and for the internal block that has been enabled, respectively. The registers used to configure the IRCC block are IR Output Mux bits located in the ECP FIFO Threshold/IR MUX located at CR0A and the UART Mode register located at CR0C. These functions may also be configured directly in the SCE registers located in the IR block. A description of these register may be found in the SMSC Infrared Communication Controller (IRCC) specification. SMSC SIO10N268 Page 169 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet 10.4.4 CR03 CR03 can only be accessed in the configuration state and after the CSR has been initialized to 03H. Table 10.6 - CR03 TYPE: R/W BIT NAME Reserved Enhance Floppy Mode 2 FDC MISCELLANEOUS DEFAULT: 0x70 on VCC POR DESCRIPTION Read Only. A read returns 0. Bit 1 Floppy Mode (Note) 0 NORMAL Floppy Mode (Default) 1 Enhanced Floppy Mode 2 (OS2) Note: Refer to the description of the TAPE DRIVE REGISTER (TDR) for more information on these modes. Read Only. A read returns 0. Bit 4 Pin DRVDEN1 Output (Note) 0 Output Programmed DRVDEN1 Value 1 Force DRVDEN1 Output High (default) Note: See Note 10.15 in section 10.4.6 CR05. IDENT is used in conjunction with MFM to define the FDC interface mode. IDENT MFM MODE 1 1 AT Mode (Default) 1 0 Reserved 0 1 PS/2 0 0 Model 30 Read Only. A read returns 0. BIT NO. 0 1 2,3 4 Reserved DRVDEN1 5 6 MFM IDENT 7 Reserved 10.4.5 CR04 CR04 can only be accessed in the configuration state and after the CSR has been initialized to 04H. Table 10.7 - CR04 TYPE: R/W BIT NAME Parallel Port Extended Modes PP AND UART MISCELLANEOUS DEFAULT: 0x00 on VCC POR DESCRIPTION Bit 1 Bit 0 If CR1 bit 3 is a low level then: 0 0 Standard and Bi-directional Modes (SPP) (default) 0 1 EPP Mode and SPP 1 0 ECP Mode (Note 10.12) 1 1 ECP Mode & EPP Mode (Note 10.11, Note 10.12) BIT NO. 1,0 Rev. 0.5 (03-24-05) Page 170 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet BIT NO. 2,3 TYPE: R/W BIT NAME Parallel Port FDC 4 5 6 7 MIDI 1 (Note 10.13) MIDI 2 ((Note 10.13) EPP Type Reserved PP AND UART MISCELLANEOUS DEFAULT: 0x00 on VCC POR DESCRIPTION Refer to Parallel Port Floppy Disk Controller description. Bit 3 Bit 2 0 0 Normal 0 1 PPFD1 1 0 PPFD2 1 1 Reserved Serial Clock Select Port 1: A low level on this bit disables MIDI support (default). A high level on this bit enables MIDI support. Serial Clock Select Port 2: A low level on this bit disables MIDI support (default). A high level on this bit enables MIDI support. 0 = EPP 1.9 (default) 1 = EPP 1.7 Reserved - Read as 0. Note 10.11 In this mode, EPP can be selected through the ecr register of ECP as mode 100. Note 10.12 In these modes, 2 drives can be supported directly, 3 or 4 drives must use external 4 drive support. SPP can be selected through the ecr register of ECP as mode 000. Note 10.13 MIDI Support: The Musical Instrumental Digital Interface (MIDI) operates at 31.25Kbaud (+/-1%). 10.4.6 CR05 CR05 can only be accessed in the configuration state and after the CSR has been initialized to 05H. Table 10.8 - CR05 FLOPPY DISK SETUP REGISTER TYPE: R/W DEFAULT: 0x00 on VCC POR BIT NAME DESCRIPTION FDC Output Type 0 = FDC Outputs are open drain (default). Control 1 = FDC Outputs are push-pull. (R/W) FDC Output 0 = FDC Outputs Active (default). Control 1 = FDC Outputs Tri-State. (R/W) FDC DMA Mode 0 = Burst mode is enabled for the FDC FIFO execution phase data transfers (default). 1 = Non-Burst mode enabled. BIT 4 BIT 3 DENSEL OUTPUT 0 0 Normal (default) 0 1 Reserved 1 0 1 1 1 0 0= do not swap (default). 1= swap drives and motor select 0 and 1 of the FDC on the parallel port. Read Only. A read returns 0. Page 171 Rev. 0.5 (03-24-05) BIT NO. 0 (Note 10.14) 1 (Note 10.14, Note 10.15) 2 4,3 DenSel 5 Swap Drives 0,1 6,7 SMSC SIO10N268 Reserved DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet Note 10.14 Bits CR05[1:0] do not affect the Parallel Port FDC. Note 10.15 In the SIO10N268, the behavior of the DRVDEN1 Control CR03.4 depends upon the FDC Output Control CR05.1 (Table 10.9). If the FDC Output Control is active DRVDEN1 will behave as follows if CR03.4 is 0 the DRVDEN1 output pin assumes the value of the DRVDEN1 function, if CR03.4 is 1 the DRVDEN1 output pin stays high. If the FDC Output Control is inactive the DRVDEN1 Control will have no affect on the DRVDEN1 output pin. Table 10.9 - DRVDEN1 Control FDC OUTPUT CONTROL (CR05.1) 0 0 1 DRVDEN1 CONTROL (CR03.4) 0 1 X DRVDEN1 (PIN 2) 1/0 1 Tristate DESCRIPTION Normal DRVDEN1 function DRVDEN1 forced high All FDD output pins are tristated 10.4.7 CR06 CR06 can only be accessed in the configuration state and after the CSR has been initialized to 06H. CR06 holds the floppy disk drive type IDs for up to four floppy disk drives (see Table 8.11 - Drive Type ID in 8.7 Floppy Disk Controller). Table 10.10 - CR06 TYPE: R/W BIT NAME ID00 ID01 ID10 ID11 ID20 ID21 ID30 ID31 DRIVE TYPE ID REGISTER DEFAULT: 0xFF on VCC POR DESCRIPTION Floppy Disk Drive 0 type ID 00. Floppy Disk Drive 0 type ID 01. Floppy Disk Drive 1 type ID 10. Floppy Disk Drive 1 type ID 11. Floppy Disk Drive 2 type ID 00. Floppy Disk Drive 2 type ID 01. Floppy Disk Drive 3 type ID 10. Floppy Disk Drive 4 type ID 11. BIT NO. 0 1 2 3 4 5 6 7 Rev. 0.5 (03-24-05) Page 172 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet 10.4.8 CR07 CR07 can only be accessed in the configuration state and after the CSR has been initialized to 07H. CR07 controls auto power management and the floppy boot drive. Table 10.11 - CR07 AUTO POWER MANAGEMENT AND BOOT DRIVE SELECT TYPE: R/W DEFAULT: 0x00 on VCC POR; Bits[7:2] = 000000b on HARD RESET BIT NAME DESCRIPTION Floppy Boot This bit is used to define the boot floppy. 0 = Drive A (default) 1 = Drive B UART 3 Enable This bit controls the AUTOPOWER DOWN feature of the UART3. The function is: 0 = Auto powerdown disabled (default) 1 = Auto powerdown enabled This bit is reset to the default state by VCC POR or a hardware reset. UART 4 Enable This bit controls the AUTOPOWER DOWN feature of the UART4. The function is: 0 = Auto powerdown disabled (default) 1 = Auto powerdown enabled This bit is reset to the default state by VCC POR or a hardware reset. Parallel Port This bit controls the AUTOPOWER DOWN feature of the Parallel Enable Port. The function is: 0 = Auto powerdown disabled (default) 1 = Auto powerdown enabled This bit is reset to the default state by VCC POR or a hardware reset. UART 2 Enable This bit controls the AUTOPOWER DOWN feature of the UART2. The function is: 0 = Auto powerdown disabled (default) 1 = Auto powerdown enabled This bit is reset to the default state by VCC POR or a hardware reset. UART 1 Enable This bit controls the AUTOPOWER DOWN feature of the UART1. The function is: 0 = Auto powerdown disabled (default) 1 = Auto powerdown enabled This bit is reset to the default state by VCC POR or a hardware reset. Floppy Disk This bit controls the AUTOPOWER DOWN feature of the Floppy Enable Disk. The function is: 0 = Auto powerdown disabled (default) 1 = Auto powerdown enabled (See note in the "FDC Power Management" section) This bit is reset to the default state by VCC POR or a hardware reset. BIT NO. 0,1 2 3 4 5 6 7 SMSC SIO10N268 Page 173 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet 10.4.9 CR08 Register CR08 is reserved. The default value of this register after power up is 00H. 10.4.10 CR09 CR09 can only be accessed in the configuration state and after the CSR has been initialized to 09H. CR09 is a test control register and all bits must be treated as Reserved. NOTE: All test modes are reserved for SMSC use. Activating test mode registers may produce undesired results. Table 10.12 - CR09 TEST 4 BIT NO. 0 1 2 3 4 5 6 7 TYPE: R/W BIT NAME Test 24 Test 25 Test 26 Test 27 Test 28 Test 29 Test 30 Test 31 DEFAULT: 0x00 on VCC POR DESCRIPTION RESERVED FOR SMSC USE 10.4.11 CR0A CR0A can only be accessed in the configuration state and after the CSR has been initialized to 0AH. CR0A defines the FIFO threshold for the ECP mode parallel port. Bits [5:4] are Reserved. Reserved bits cannot be written and return 0 when read. Bits [7:6] are the IR OUTPUT MUX bits and are reset to the default state by a POR and a hardware reset. Table 10.13 - CR0A TYPE: R/W BIT NO. 0 1 2 3 4,5 BIT NAME THR0 THR1 THR2 THR3 Reserved ECP FIFO THRESHOLD/IR MUX DEFAULT: 0x00 on VCC POR; Bits[7:6] = 00 on HARD RESET DESCRIPTION ECP FIFO Threshold 0. ECP FIFO Threshold 1. ECP FIFO Threshold 2. ECP FIFO Threshold 3. Read Only. A read returns 0. Rev. 0.5 (03-24-05) Page 174 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet TYPE: R/W BIT NO. 6,7 BIT NAME IR Output Mux ECP FIFO THRESHOLD/IR MUX DEFAULT: 0x00 on VCC POR; Bits[7:6] = 00 on HARD RESET DESCRIPTION These bits are used to select IR Output Mux Mode. BIT7 BIT6 MUX MODE 0 0 Active device to COM port (Default). That is, depending on the mode of Serial Port 2, use Pins 90-97 for COM signals or use RXD2 and TXD2 (pins 92 and 93) for IR. When Serial Port 2 is inactive (UART2 Power bit = 0), then TXD2 signal is tristate. The IRTX2 signal is low. 0 1 Active device to IR port. That is, use IRRX2, IRTX2 (pins 60, 61). When Serial Port 2 is inactive (UART2 Power bit = 0), then IRTX2 signal is low. The TXD2 signal is low. 1 0 Reserved. 1 1 Outputs Inactive: TXD2/IRTX and IRTX2 are High-Z, regardless of mode of UART2 and state of UART2 powerdown bit. 10.4.12 CR0B CR0B can only be accessed in the configuration state and after the CSR has been initialized to 0BH. CR0B indicates the Drive Rate table (Table 10.15) used for each drive. Refer to section CR1F for the Drive Type register. Table 10.14 - CR0B DRIVE RATE BIT NO. 0 1 2 3 4 5 6 7 TYPE: R/W BIT NAME DTR0 DTR1 DTR0 DTR1 DTR0 DTR1 DTR0 DTR1 DEFAULT: 0x00 on VCC POR DESCRIPTION Floppy Disk Drive 0 Drive Rate Table Bit 0. Floppy Disk Drive 0 Drive Rate Table Bit 1. Floppy Disk Drive 1 Drive Rate Table Bit 0. Floppy Disk Drive 1 Drive Rate Table Bit 1. Floppy Disk Drive 2 Drive Rate Table Bit 0. Floppy Disk Drive 2 Drive Rate Table Bit 1. Floppy Disk Drive 3 Drive Rate Table Bit 0. Floppy Disk Drive 3 Drive Rate Table Bit 1. Table 10.15 - Drive Rate Table (Recommended) DRT1 0 0 1 1 DRT0 0 1 0 1 FORMAT 360K, 1.2M, 720K, 1.44M and 2.88M Vertical Format 3-Mode Drive 2 Meg Tape Reserved SMSC SIO10N268 Page 175 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet 10.4.13 CR0C CR0C can only be accessed in the configuration state and after the CSR has been initialized to 0CH. CR0C controls the operating mode of the UART. This register is reset to the default state by a POR or a hardware reset. Table 10.16 - CR0C TYPE: R/W BIT NAME UART 2 RCV Polarity UART 2 XMIT Polarity UART 2 Duplex BIT NO. 0 1 2 3, 4, 5 UART 2 MODE 6 UART 1 Speed 7 UART 2 Speed UART MODE DEFAULT: 0x02 on VCC POR and HARD RESET DESCRIPTION 0 = RX input active high (default). 1 = RX input active low. 0 = TX output active high. 1 = TX output active low (default). This bit is used to define the FULL/HALF DUPLEX operation of UART 2. 1 = Half duplex 0 = Full duplex (default) UART 2 Mode (Note 10.16) 543 000 Standard COM Functionality (default) 001 IrDA (HPSIR) 010 Amplitude Shift Keyed IR 011 Reserved (Note 10.17) 1xx Reserved (Note 10.17) This bit enables the high speed mode of UART 1. 1 = High speed enabled 0 = Standard (default) This bit enables the high speed mode of UART 2. 1 = High speed enabled 0 = Standard (default) Note 10.16 The UART 2 Mode may be selected by writing bits[5:3] shown or by programming the block control bits located in Register Block One - SCE Configuration Register A of the SCE (FIR) block. See the IrCC Specification dated 5/10/96 for a detailed description of this register and the modes supported. Note 10.17 Writing these reserved bit combinations will place the IR block into an alternate mode, which is beyond the scope of this specification. Users that require these advanced options should refer to the IrCC Specification dated 5/10/96. 10.4.14 CR0D CR0D can only be accessed in the configuration state and after the CSR has been initialized to 0DH. This register is read only. CR0D contains the SIO10N268 Device ID. The default value of this register after power up is 5BH on VCC POR. 10.4.15 CR0E CR0E can only be accessed in the configuration state and after the CSR has been initialized to 0EH. This register is read only. CR0E contains the current SIO10N268 Chip Revision Level starting at 00H. Rev. 0.5 (03-24-05) Page 176 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet 10.4.16 CR0F CR0F can only be accessed in the configuration state and after the CSR has been initialized to 0FH. CR0F is a test control register and all bits must be treated as Reserved. NOTE: All test modes are reserved for SMSC use. Activating test mode registers may produce undesired results. Table 10.17 - CR0F TEST 1 BIT NO. 0 1 2 3 4 5 6 7 TYPE: R/W BIT NAME Test 0 Test 1 Test 2 Test 3 Test 4 Test 5 Test 6 Test 7 DEFAULT: 0x00 on VCC POR DESCRIPTION RESERVED FOR SMSC USE 10.4.17 CR10 CR10 can only be accessed in the configuration state and after the CSR has been initialized to 10H. CR10 is a test control register and all bits must be treated as Reserved. NOTE: All test modes are reserved for SMSC use. Activating test mode registers may produce undesired results. Table 10.18 - CR10 TEST 2 BIT NO. 0 1 2 3 4 5 6 7 TYPE: R/W BIT NAME Test 8 Test 9 Test 10 Test 11 Test 12 Test 13 Test 14 Test 15 DEFAULT: 0x00 on VCC POR DESCRIPTION RESERVED FOR SMSC USE 10.4.18 CR11 CR11 can only be accessed in the configuration state and after the CSR has been initialized to 11H. CR11 is a test control register and all bits must be treated as Reserved. NOTE: All test modes are reserved for SMSC use. Activating test mode registers may produce undesired results. SMSC SIO10N268 Page 177 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet Table 10.19 - CR11 TEST 3 BIT NO. 0 1 2 3 4 5 6 7 TYPE: R/W BIT NAME Test 16 Test 17 Test 18 Test 19 Test 20 Test 21 Test 22 Test 23 DEFAULT: 0x00 on VCC POR DESCRIPTION RESERVED FOR SMSC USE 10.4.19 CR12 - CR13 CR12 and CR13 are the SIO10N268 Configuration Ports base address registers (Table 10.20 and Table 10.21). These registers are used to relocate the Configuration Ports base address beyond the power-up defaults determined by the SYSOPT pin programming. CR12 contains the Configuration Ports base address bits A[7:0]. CR13 contains the Configuration Ports base address bits A[10:8]. The address bits A[15:11] must be `00000' to access the configuration port. The Configuration Ports base address is relocatable on even-byte boundaries; i.e., A0 = `0'. At power-up the Configuration Ports base address is determined by the SYSOPT pin programming. To relocate the Configuration Ports base address after power-up, first write the lower address bits of the new base address to CR12 and then write the upper address bits to CR13. NOTE: Writing CR13 changes the Configuration Ports base address. Table 10.20 - CR12 CONFIGURATION PORTS BASE ADDRESS BYTE 0 (Note 10.18) DEFAULT: 0x2E (SYSOPT=0) TYPE: R/W 0x4E (SYSOPT=1) on VCC POR and HARD RESET BIT NAME DESCRIPTION Reserved Read Only. A read returns 0. A1 A2 A3 Configuration Ports Base Address Byte 0 for decoder. A4 A5 A6 A7 BIT NO. 0 1 2 3 4 5 6 7 Note 10.18 The Configuration Ports Base Address is relocatable on even-byte boundaries; i.e., A0 = "0". Rev. 0.5 (03-24-05) Page 178 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet Table 10.21 - CR13 CONFIGURATION PORTS BASE ADDRESS BYTE 1 (Note 10.19) DEFAULT: 0x00 (SYSOPT=0) TYPE: R/W 0x00 (SYSOPT=1) on VCC POR and HARD RESET BIT NAME DESCRIPTION A8 Configuration Ports Base Address Byte 1 for decoder. A9 A10 Reserved Read Only. A read returns 0. BIT NO. 0 1 2 3-7 Note 10.19 Writing CR13 changes the Configuration Ports base address. 10.4.20 CR14 CR14 can only be accessed in the configuration state and after the CSR has been initialized to 14H. CR14 shadows the bits in the write-only FDC run-time DSR register. Table 10.22 - CR14 DSR SHADOW REGISTER BIT NO. 0,1 2-4 5 6 7 TYPE: R BIT NAME Data Rate Select 0-1 PRECOMP 0-2 Reserved PWRDOWN SOFTRESET DEFAULT: N/A DESCRIPTION These bits the data rate of the floppy controller. These three bits select the value of write precompensation that will be applied to the WDATA output signal Read Only. A read returns 0. A logic "1" written to this bit will put the floppy controller into manual low power mode A logic "0" written to this bit resets the floppy disk controller. This bit is self clearing. 10.4.21 CR15 CR15 can only be accessed in the configuration state and after the CSR has been initialized to 15H. CR15 shadows the bits in the write-only UART1 run-time FCR register. Table 10.23 - CR15 UART1 FCR SHADOW REGISTER TYPE: R (Note 10.20) DEFAULT: N/A BIT NO. 0 1 BIT NAME FIFO Enable RCVR FIFO Reset DESCRIPTION Setting this bit to a logic "1" enables both the XMIT and RCVR FIFOs Setting this bit to a logic "1" clears all bytes in the RCVR FIFO and resets its counter logic to 0. This bit is self clearing. SMSC SIO10N268 Page 179 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet UART1 FCR SHADOW REGISTER TYPE: R (Note 10.20) DEFAULT: N/A BIT NO. 2 3 4,5 6,7 BIT NAME DESCRIPTION XMIT FIFO Reset Setting this bit to a logic "1" clears all bytes in the XMIT FIFO and resets its counter logic to 0. This bit is self-clearing. DMA Mode Writing to this bit has no effect on the operation of the UART. Select Reserved Read Only. A read returns 0. RCVR Trigger These bits are used to set the trigger level for the RCVR FIFO interrupt. BIT7 BIT6 RCVR FIFO Trigger Level (BYTES) 0 0 1 0 1 4 1 0 8 1 1 14 Note 10.20 This is a read only register. Software may set these register bits by writing the UART1 runtime FCR register located at an offset of +2 from the UART1 Base I/O Address. See Table 10.86 - I/O Base Address Configuration Register Description. 10.4.22 CR16 CR16 can only be accessed in the configuration state and after the CSR has been initialized to 16H. CR16 shadows the bits in the write-only UART2 run-time FCR register. See CR15 for register description. NOTE: This is a read only register. Software may set these register bits by writing the UART2 runtime FCR register located at an offset of +2 from the UART2 Base I/O Address. See Table 10.86 - I/O Base Address Configuration Register Description. Rev. 0.5 (03-24-05) Page 180 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet 10.4.23 CR17 CR17 can only be accessed in the configuration state and after the CSR has been initialized to 17H. CR17 is the Force FDD Status Change register. Table 10.24 - CR17 FORCE FDD STATUS CHANGE REGISTER TYPE: R/W DEFAULT: 0x03 on VCC POR and Hard Reset BIT NAME DESCRIPTION Force DSKCHG 0-1 Setting either of the Force Disk Change bits active (1) forces the FDD nDSKCHG input active when the appropriate drive has been selected. FORCE DSKCHG1 and FORCE DSKCHG0 can be written to a 1 but are not clearable by software. FORCE DSKCHG1 is cleared on (nSTEP AND nDS1), FORCE DSKCHG0 is cleared on (nSTEP AND nDS0). Note: The DSK CHG bit in the Floppy DIR register, Bit 7 = (nDS0 AND FORCE DSKCHG0) OR (nDS1 AND FORCE DSKCHG1) OR nDSKCHG. Setting either of the Force Disk Change bits active (1) forces the FDD nDSKCHG input active when the appropriate drive has been selected. Bit[0] Force Change for FDC0 0=Inactive 1=Active Bit[1] Force Change for FDC1 0=Inactive 1=Active Force WRTPRT FORCE WRTPRT asserts the internal nWRTPRT input to the controller when the FORCE WRTPRT bit is active ("1") and a drive has been selected. The FORCE WRTPRT function applies to the nWRTPRT pin in the FDD Interface as well as the nWRTPRT pin in the Parallel Port FDC. Reserved Read Only. A read returns 0. BIT NO. 0,1 2 3-7 NOTE: The controls in the Force FDD Status Change register (CR17) apply to the FDD Interface pins as well as to the Parallel Port FDC. 10.4.24 CR18 CR18 can only be accessed in the configuration state and after the CSR has been initialized to 18H. Table 10.25 - CR18 UART 3,4 MISCELLANEOUS DEFAULT: 0x00 on VCC POR, TYPE: R/W bits[6:7] are reset on Hard Reset BIT NAME DESCRIPTION Reserved Reserved - Read as 0. MIDI 3 (Note Serial Clock Select Port 3: A low level on this bit disables MIDI support (default). A high level on this bit enables MIDI support. 10.21) MIDI 4 (Note 10.21) Serial Clock Select Port 4: A low level on this bit disables MIDI support (default). A high level on this bit enables MIDI support. BIT NO. 0-3 4 5 SMSC SIO10N268 Page 181 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet BIT NO. 6 7 UART 3,4 MISCELLANEOUS DEFAULT: 0x00 on VCC POR, TYPE: R/W bits[6:7] are reset on Hard Reset BIT NAME DESCRIPTION UART 3 This bit enables the high speed mode of UART 3. Speed 1 = High speed enabled 0 = Standard (default) UART 4 This bit enables the high speed mode of UART 4. Speed 1 = High speed enabled 0 = Standard (default) Note 10.21 MIDI Support: The Musical Instrumental Digital Interface (MIDI) operates at 31.25Kbaud (+/-1%). 10.4.25 CR19 CR19 can only be accessed in the configuration state and after the CSR has been initialized to 19H. CR19 shadows the bits in the write-only UART3 run-time FCR register. Table 10.26 - CR19 UART3 FCR SHADOW REGISTER TYPE: R (Note 10.22) DEFAULT: N/A BIT NO. 0 1 2 3 4,5 6,7 BIT NAME FIFO Enable RCVR FIFO Reset XMIT FIFO Reset DMA Mode Select Reserved RCVR Trigger DESCRIPTION Setting this bit to a logic "1" enables both the XMIT and RCVR FIFOs Setting this bit to a logic "1" clears all bytes in the RCVR FIFO and resets its counter logic to 0. This bit is self clearing. Setting this bit to a logic "1" clears all bytes in the XMIT FIFO and resets its counter logic to 0. This bit is self-clearing. Writing to this bit has no effect on the operation of the UART. Read Only. A read returns 0. These bits are used to set the trigger level for the RCVR FIFO interrupt. BIT7 BIT6 RCVR FIFO Trigger Level (BYTES) 0 0 1 0 1 4 1 0 8 1 1 14 Note 10.22 This is a read only register. Software may set these register bits by writing the UART3 runtime FCR register located at an offset of +2 from the UART3 Base I/O Address. See Table 10.86 - I/O Base Address Configuration Register Description. Rev. 0.5 (03-24-05) Page 182 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet 10.4.26 CR1A CR1A can only be accessed in the configuration state and after the CSR has been initialized to 1AH. CR1A shadows the bits in the write-only UART4 run-time FCR register. Table 10.27 - CR1A UART4 FCR SHADOW REGISTER TYPE: R (Note 10.23) DEFAULT: N/A BIT NO. 0 1 2 3 4,5 6,7 BIT NAME FIFO Enable RCVR FIFO Reset XMIT FIFO Reset DMA Mode Select Reserved RCVR Trigger DESCRIPTION Setting this bit to a logic "1" enables both the XMIT and RCVR FIFOs Setting this bit to a logic "1" clears all bytes in the RCVR FIFO and resets its counter logic to 0. This bit is self clearing. Setting this bit to a logic "1" clears all bytes in the XMIT FIFO and resets its counter logic to 0. This bit is self-clearing. Writing to this bit has no effect on the operation of the UART. Read Only. A read returns 0. These bits are used to set the trigger level for the RCVR FIFO interrupt. BIT7 BIT6 RCVR FIFO Trigger Level (BYTES) 0 0 1 0 1 4 1 0 8 1 1 14 Note 10.23 This is a read only register. Software may set these register bits by writing the UART4 runtime FCR register located at an offset of +2 from the UART4 Base I/O Address. See Table 10.86 - I/O Base Address Configuration Register Description. 10.4.27 CR1B CR1B can only be accessed in the configuration state and after the CSR has been initialized to 1BH. CR1B is used to select the base address of Serial Port 3 (UART3). The serial port can be set to 96 locations on 8-byte boundaries from 100H - 3F8H. To disable Serial Port 3, set ADR9 and ADR8 to zero. Set CR1B.0 to 0 when writing the UART3 Base Address. Serial Port 3 Address Decoding: address bits A[15:10] must be `000000' to access UART3 registers. A[2:0] are decoded as XXXb. Table 10.28 - CR1B TYPE: R/W BIT NAME Reserved ADR3 ADR4 ADR5 ADR6 ADR7 ADR8 UART3 BASE ADDRESS REGISTER DEFAULT: 0x00 on VCC POR DESCRIPTION Read Only. A read returns 0. Serial Port 3 Base Address bits for decoder. BIT NO. 0 1 2 3 4 5 6 SMSC SIO10N268 Page 183 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet BIT NO. 7 TYPE: R/W BIT NAME ADR9 UART3 BASE ADDRESS REGISTER DEFAULT: 0x00 on VCC POR DESCRIPTION 10.4.28 CR1C CR1C can only be accessed in the configuration state and after the CSR has been initialized to 1CH. CR1C is used to select the base address of Serial Port 4 (UART4). The serial port can be set to 96 locations on 8-byte boundaries from 100H - 3F8H. To disable Serial Port 4, set ADR9 and ADR8 to zero. Set CR1C.0 to 0 when writing the UART4 Base Address. Serial Port 4 Address Decoding: address bits A[15:10] must be `000000' to access UART4 registers. A[2:0] are decoded as XXXb. Table 10.29 - CR1C UART4 BASE ADDRESS REGISTER TYPE: R/W DEFAULT: 0x00 on VCC POR BIT NAME DESCRIPTION Reserved Read Only. A read returns 0. ADR3 ADR4 ADR5 Serial Port 4 Base Address bits for decoder. ADR6 ADR7 ADR8 ADR9 BIT NO. 0 1 2 3 4 5 6 7 10.4.29 CR1D CR1D can only be accessed in the configuration state and after the CSR has been initialized to 1DH. CR1D is used to select the IRQ for Serial Port 3 (bits 7 - 4) and for Serial Port 4 (bits 3 - 0). Refer to the IRQ encoding for CR27. Any unselected IRQ output is in tristate. Shared IRQs are not supported in the SIO10N268. Table 10.30 - CR1D UART 3, 4 INTERRUPT SELECTION DEFAULT: 0x00 on VCC POR DESCRIPTION These bits are used to select IRQ for Serial Port 4. See IRQ encoding for CR27. UART3 IRQ Select These bits are used to select IRQ for Serial Port 3. See IRQ encoding for CR27. TYPE: R/W BIT NAME UART4 IRQ Select BIT NO. 0-3 4-7 Rev. 0.5 (03-24-05) Page 184 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet Table 10.31 - UART Interrupt Operation UARTX UARTX OUT2 BIT 0 1 1 NOTE: UARTX IRQ OUTPUT STATE Z asserted de-asserted IRQ UARTX IRQ STATE Z 1 0 It is the responsibility of the software to ensure that two IRQ's are not set to the same IRQ number. Potential damage to chip may result. Z = Don't Care. NOTE: 10.4.30 CR1E CR1E can only be accessed in the Configuration State and after the CSR has been initialized to 1EH. Table 10.32 - CR1E TYPE: R/W BIT NAME CLOCKI32 CLOCK/AEN CONTROL REGISTER DEFAULT: 0x00 on VTR POR DESCRIPTION Bit[0] (CLK32_PRSN) 0=32kHz clock is connected to the CLKI32 pin (default) 1=32kHz clock is not connected to the CLKI32 pin (pin is grounded) AEN Control bit 0=Internal AEN signal should be asserted if the AEN pin is high OR if SA[0:15]=0000h. 1=Internal AEN signal should be asserted only if the AEN pin is high. Reserved - Read as 0. BIT NO. 0 1 AEN Control 2-7 Reserved 10.4.31 CR1F CR1F can only be accessed in the configuration state and after the CSR has been initialized to 1FH. CR1F indicates the floppy disk Drive Type for each of four floppy disk drives. The floppy disk Drive Type is used to map the three FDC DENSEL, DRATE1 and DRATE0 outputs onto two Super I/O output pins DRVDEN1 and DRVDEN0 (Table 10.34). Table 10.33 - CR1F DRIVE TYPE BIT NO. 0 1 2 TYPE: R/W BIT NAME DT1 DT0 DT1 DEFAULT: 0x00 on VCC POR DESCRIPTION Drive Type Bit 1 for FDD 0. Drive Type Bit 0 for FDD 0. Drive Type Bit 1 for FDD 1. SMSC SIO10N268 Page 185 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet DRIVE TYPE BIT NO. 3 4 5 6 7 TYPE: R/W BIT NAME DT0 DT1 DT0 DT1 DT0 DEFAULT: 0x00 on VCC POR DESCRIPTION Drive Type Bit 0 for FDD 1. Drive Type Bit 1 for FDD 2. Drive Type Bit 0 for FDD 2. Drive Type Bit 1 for FDD 3. Drive Type Bit 0 for FDD 3. Table 10.34 - Drive Type Encoding DRIVE TYPE DT0 DT1 0 0 DRVDEN0 DENSEL DRVDEN1 DRATE0 DRIVE TYPE DESCRIPTION 4/2/1 MB 3.5" 2/1 MB 5.25" FDDS 2/1.6/1 MB 3.5" (3-MODE) PS/2 0 1 1 1 0 1 DRATE1 nDENSEL DRATE0 DRATE0 DRATE0 DRATE1 10.4.32 CR20 CR20 can only be accessed in the configuration state and after the CSR has been initialized to 20H. CR20 is used to select the base address of the floppy disk controller (FDC). The FDC base address can be set to 48 locations on 16 byte boundaries from 100H - 3F8H. To disable the FDC set ADR9 and ADR8 to zero. Set CR20.[1:0] to 00b when writing the FDC Base Address. FDC Address Decoding: address bits A[15:10] must be `000000' to access the FDC registers. A[3:0] are decoded as 0XXXb. Table 10.35 - CR20 TYPE: R/W BIT NAME Reserved Reserved ADR4 ADR5 ADR6 ADR7 ADR8 ADR9 FDC BASE ADDRESS DEFAULT: 0x3C on VCC POR DESCRIPTION Read Only. A read returns 0. Read Only. A read returns 0. FDC Base Address bits for decoder. BIT NO. 0 1 2 3 4 5 6 7 Rev. 0.5 (03-24-05) Page 186 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet 10.4.33 CR21 CR21 can only be accessed in the configuration state and after the CSR has been initialized to 21H. CR21 is the Floppy on Parallel Port Pin register. Table 10.36 - CR21 FDC ON PP/EPP TIMEOUT SELECT DEFAULT: 0x00 on VCC POR DESCRIPTION FDC ON PARALLEL PORT PIN BIT1 BIT0 DESCRIPTION 0 0 Bits in PP mode Register control the FDC on the parallel port, the FDC_PP pin function is not used. 0 1 The FDC_PP pin controls the FDC on the PP as follows: (non-inverted polarity) when the pin is low, the parallel port pins are used for a floppy disk controller: drive 0 is on FDC pins, drive 1 is on parallel port pins. 1 0 The FDC_PP pin controls the FDC on the PP as follows: (non-inverted polarity) when the pin is low, the parallel port pins are used for a floppy disk controller: drive 0 is on parallel port pins and drive 1 is on parallel port pins. 1 1 Reserved TIMEOUT_S This bit selects the means of clearing the TIMEOUT bit in the EPP Status ELECT register. If the TIMEOUT_SELECT bit is cleared (`0'), the TIMEOUT bit is cleared on the trailing edge of the read of the EPP Status Register (default). If the TIMEOUT_SELECT bit is set (`1'), the TIMEOUT bit is cleared on a write of `1' to the TIMEOUT bit. Reserved Read Only. A read returns 0. TYPE: R/W BIT NAME FDC_PP BIT NO. 0,1 2 3-7 10.4.34 CR22 The ECP Software Select register CR22 contains the ECP IRQ Select bits and the ECP DMA Select bits. CR22 is part of the ECP DMA/IRQ Software Indicators described in the ECP cnfgB register. CR22 is read/write. NOTE: All of the ECP DMA/IRQ Software Indicators, including CR22, are software-only. Writing these bits does not affect the ECP hardware DMA or IRQ channels that are configured in CR26 and CR27. Table 10.37 - CR22 ECP SOFTWARE SELECT REGISTER TYPE: R/W DEFAULT: 0x00 on VCC POR and Hard Reset BIT NAME DESCRIPTION ECP DMA Select ECP DMA software Indicator ECP IRQ Select ECP IRQ Software Indicator Reserved Read Only. A read returns 0. BIT NO. 2:0 5:3 6,7 SMSC SIO10N268 Page 187 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet 10.4.35 CR23 CR23 can only be accessed in the configuration state and after the CSR has been initialized to 23H. CR23 is used to select the base address of the parallel port. If EPP is not enabled, the parallel port can be set to 192 locations on 4-byte boundaries from 100H - 3FCH; if EPP is enabled, the parallel port can be set to 96 locations on 8-byte boundaries from 100H - 3F8H. To disable the parallel port, set ADR9 and ADR8 to zero. Parallel Port Address Decoding: address bits A[15:10] must be `000000' to access the Parallel Port when in Compatible, Bi-directional, or EPP modes. A10 is active when in ECP mode. Table 10.38 - CR23 TYPE: R/W BIT NAME ADR2 ADR3 ADR4 ADR5 ADR6 ADR7 ADR8 ADR9 PARALLEL PORT BASE ADDRESS DEFAULT: 0x00 on VCC POR DESCRIPTION BIT NO. 0 1 2 3 4 5 6 7 Parallel Port Base Address bits for decoder. Table 10.39 - Parallel Port Addressing Options EPP ENABLED No Yes ADDRESSING (LOW BITS) DECODE A[1:0] = XXb A[2:0] = XXXb 10.4.36 CR24 CR24 can only be accessed in the configuration state and after the CSR has been initialized to 24H. CR24 is used to select the base address of Serial Port 1 (UART1). The serial port can be set to 96 locations on 8-byte boundaries from 100H - 3F8H. To disable Serial Port 1, set ADR9 and ADR8 to zero. Set CR24.0 to 0 when writing the UART1 Base Address. Serial Port 1 Address Decoding: address bits A[15:10] must be `000000' to access UART1 registers. A[2:0] are decoded as XXXb. Table 10.40 - CR24 TYPE: R/W BIT NAME Reserved ADR3 ADR4 ADR5 ADR6 ADR7 UART1 BASE ADDRESS REGISTER DEFAULT: 0x00 on VCC POR DESCRIPTION Read Only. A read returns 0. Serial Port 1 Base Address bits for decoder. BIT NO. 0 1 2 3 4 5 Rev. 0.5 (03-24-05) Page 188 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet 6 7 ADR8 ADR9 10.4.37 CR25 CR25 can only be accessed in the configuration state and after the CSR has been initialized to 25H. CR25 is used to select the base address of Serial Port 2 (UART2). Serial Port 2 can be set to 96 locations on 8byte boundaries from 100H - 3F8H. To disable Serial Port 2, set ADR9 and ADR8 to zero. Set CR25.0 to 0 when writing the UART2 Base Address. Serial Port 2 Address Decoding: address bits A[15:10] must be `000000' to access UART2 registers. A[2:0] are decoded as XXXb. Table 10.41 - CR25 TYPE: R/W BIT NAME Reserved ADR3 ADR4 ADR5 ADR6 ADR7 ADR8 ADR9 UART2 BASE ADDRESS REGISTER DEFAULT: 0x00 on VCC POR DESCRIPTION Read Only. A read returns 0. BIT NO. 0 1 2 3 4 5 6 7 Serial Port 2 Base Address bits for decoder. 10.4.38 CR26 CR26 can only be accessed in the configuration state and after the CSR has been initialized to 26H. CR26 is used to select the DMA for the FDC (Bits 4 - 7) and the Parallel Port (bits 0 - 3). Any unselected DMA Request output (DRQ) is in tristate. Table 10.42 - CR26 FDC AND PP DMA SELECTION REGISTER TYPE: R/W DEFAULT: 0xFF on VCC POR BIT NAME DESCRIPTION PP DMA Select These bits are used to select DMA for Parallel Port. FDC DMA Select These bits are used to select DMA for Floppy Disk Controller. Table 10.43 - DMA Selection BITS[3:0] OR BITS[7:4] 0000 0001 0010 0011 0100 DMA SELECTED DMA0 DMA1 DMA2 (Note 10.24) DMA3 Reserved BIT NO. 3:0 7:4 SMSC SIO10N268 Page 189 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet .... .... 1110 1111 .... .... Reserved None Note 10.24 In LPC_MODE the FDC must be assigned to DMA Channel 2. 10.4.39 CR27 CR27 can only be accessed in the configuration state and after the CSR has been initialized to 27H. CR27 is used to select the IRQ for the FDC (Bits 4 - 7) and the Parallel Port (bits 3 - 0). Any unselected IRQ output (registers CR27 - CR29) is in tri-state. Table 10.44 - CR27 FDC AND PP IRQ SELECTION REGISTER TYPE: R/W DEFAULT: 0x00 on VCC POR BIT NAME DESCRIPTION PP IRQ Select These bits are used to select IRQ for Parallel Port. FDC IRQ Select These bits are used to select IRQ for Floppy Disk Controller. Table 10.45 - IRQ Encoding BITS[3:0] OR BITS[7:4] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 IRQ SELECTED NONE IRQ_1 IRQ_2 IRQ_3 IRQ_4 IRQ_5 IRQ_6 IRQ_7 IRQ_8 IRQ_9 IRQ_10 IRQ_11 IRQ_12 IRQ_13 IRQ_14 IRQ_15 BIT NO. 3:0 7:4 10.4.40 CR28 CR28 can only be accessed in the configuration state and after the CSR has been initialized to 28H. CR28 is used to select the IRQ for Serial Port 1 (bits 7 - 4) and for Serial Port 2 (bits 3 - 0). Refer to the IRQ encoding for CR27 (Table 10.45). Any unselected IRQ output (registers CR27 - CR29) is in tristate. Shared IRQs are not supported in the SIO10N268. Rev. 0.5 (03-24-05) Page 190 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet Table 10.46 - CR28 TYPE: R/W BIT NAME UART2 IRQ Select UART1 IRQ Select UART INTERRUPT SELECTION DEFAULT: 0x00 on VCC POR DESCRIPTION These bits are used to select IRQ for Serial Port 2. See IRQ encoding for CR27 (Table 10.45 - IRQ Encoding). These bits are used to select IRQ for Serial Port 1. See IRQ encoding for CR27 (Table 10.45 - IRQ Encoding). BIT NO. 3:0 7:4 Table 10.47 - UART Interrupt Operation UARTX UARTX IRQ UARTX OUTPUT OUT2 BIT STATE 0 Z 1 asserted 1 de-asserted NOTE: IRQ UARTX IRQ STATE Z 1 0 It is the responsibility of the software to ensure that two IRQ's are not set to the same IRQ number. Potential damage to chip may result. Z = Don't Care. NOTE: 10.4.41 CR29 CR29 can only be accessed in the configuration state and after the CSR has been initialized to 29H. CR29 controls the HPMODE bit and is used to select the IRQ mapping (bits 0 - 3) for the IRQIN1 pin. Refer to IRQ encoding for CR27 (Table 10.45). Any unselected IRQ output (registers CR27 - CR29) is in tristate. Table 10.48 - CR29 IRQIN1/HPMODE/SIRQ_CLKRUN_En TYPE: R/W DEFAULT: 0x80 on VCC POR BIT NAME DESCRIPTION IRQIN1 Selects the IRQ for IRQIN1. (See Application Note in the "Routable IRQ Inputs" section) HPMODE See Figure 8.8 - Infrared Interface Block Diagram 0 Select IRMODE (default) 1 Select IRRX3 RESERVED Not Writeable, Reads Return "0" SIRQ_CLKRUN_EN Serial IRQ and CLKRUN enable bit. 0 = Disable 1 = Enable (default) BIT NO. 0-3 4 5-6 7 10.4.42 CR2A CR2A can only be accessed in the configuration state and after the CSR has been initialized to 2AH. CR2A is used to select the IRQ mapping for the IRQIN2 and IRQIN3 pins. Refer to IRQ encoding for CR27. Any unselected IRQ output (registers CR27 - CR29) is in tristate. SMSC SIO10N268 Page 191 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet Table 10.49 - CR2A IRQIN2 BIT NO. 0-3 4-7 TYPE: R/W BIT NAME IRQIN2 IRQIN3 DEFAULT: 0x00 on VCC POR DESCRIPTION Selects the IRQ for IRQIN2. Selects the IRQ for IRQIN3. 10.4.43 CR2B CR2B can only be accessed in the configuration state and after the CSR has been initialized to 2BH. CR2B is used to set the SCE (FIR) base address ADR[10:3]. The SCE base address can be set to 224 locations on 8-byte boundaries from 100H - 7F8H. To disable the SCE, set ADR10, ADR9 and ADR8 to zero. SCE Address Decoding: address bits A[15:11] must be `00000' to access SCE registers. A[2:0] are decoded as XXXb. Table 10.50 - CR2B SCE (FIR) BASE ADDRESS REGISTER TYPE: R/W DEFAULT: 0x00 on VCC POR BIT NAME DESCRIPTION ADR3 ADR4 ADR5 ADR6 FIR Base Address bits for decoder. ADR7 ADR8 ADR9 ADR10 BIT NO. 0 1 2 3 4 5 6 7 10.4.44 CR2C CR2C can only be accessed in the configuration state and after the CSR has been initialized to 2CH. Bits D[3:0] of this register are used to select the DMA for the SCE (FIR). Bits D[7:4] are Reserved. Reserved bits cannot be written and return 0 when read. Any unselected DMA Request output (DRQ) is in tristate. Rev. 0.5 (03-24-05) Page 192 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet Table 10.51 - CR2C TYPE: R/W BIT NAME DMA Select SCE (FIR) DMA SELECT REGISTER DEFAULT: 0x0F on VCC POR DESCRIPTION BIT3 BIT2 BIT1 BIT0 DMA SELECTED 0 0 0 0 DMA0 0 0 0 1 DMA1 0 0 1 0 DMA2 (Note 10.25) 0 0 1 1 DMA3 0 1 0 0 RESERVED . . . . . . . . . . 1 1 1 0 RESERVED 1 1 1 1 NONE Read Only. A read returns 0. BIT NO. 3:0 7:4 Reserved Note 10.25 In LPC_MODE the FDC must be assigned to DMA Channel 2. 10.4.45 CR2D CR2D can only be accessed in the configuration state and after the CSR has been initialized to 2DH. CR2D is used to set the IR Half Duplex Turnaround Delay Time for the IR port. This value is 0 to 25.5msec in 100sec increments. The IRCC v2.0 block includes an 8 bit IR Half Duplex Time-out register in SCE Register Block 5, Address 1 that interacts with configuration register CR2D. These two registers behave like the other IRCC Legacy controls where either source uniformly updates the value of both registers when either register is explicitly written using IOW or following a device-level POR. IRCC software resets do not affect these registers. The IR Half Duplex Time-out is programmable from 0 to 25.5mS in 100S increments, as follows: IR HALF DUPLEX TIME-OUT = (CR2D) x 100S Table 10.52 - CR2D TYPE: R/W BIT NAME IR Half Duplex Time Out IR HALF DUPLEX TIMEOUT DEFAULT: 0x03 on VCC POR DESCRIPTION These bits are used to set the IR Half Duplex Turnaround Delay Time for the IR port. This value is 0 to 25.5msec in 100sec increments. BIT NO. 0-7 SMSC SIO10N268 Page 193 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet 10.4.46 CR2E CR2E can only be accessed in the configuration state and after the CSR has been initialized to 2EH. CR2E is directly connected to SCE Register Block Three, Address 0x05 in the IRCC v2.0 block. Table 10.53 - CR2E SOFTWARE SELECT A TYPE: R/W DEFAULT: 0x00 on VCC POR BIT NAME DESCRIPTION Software Select A These bits are directly connected to SCE Register Block Three, Address 0x05 in the IRCC v2.0 block. BIT NO. 0-7 10.4.47 CR2F CR2F can only be accessed in the configuration state and after the CSR has been initialized to 2FH. CR2F is directly connected to SCE Register Block Three, Address 0x06 in the IRCC v2.0 block. Table 10.54 - CR2F SOFTWARE SELECT B TYPE: R/W DEFAULT: 0x00 on VCC POR BIT NAME DESCRIPTION Software Select B These bits are directly connected to SCE Register Block Three, Address 0x06 in the IRCC v2.0 block. BIT NO. 0-7 10.4.48 CR30 CR30 can only be accessed in the configuration state and after the CSR has been initialized to 30H. CR30 is used to set the Runtime Register Block base address ADR[11:5]. The Runtime Register Block base address can be set to 120 locations on 32-byte boundaries from 100H - FE0H. To disable Runtime Registers Block set the Base Address to a value below 100h (i.e., set ADR11 - ADR8 to zero). Runtime Register Address Decoding: To access registers located in the Runtime Register block the I/O address bits A[15:12] must be `0000' and the address bits A[11:5] must match the value programmed in the Base Address Register below. I/O address bits A[4:0] are used as the register offset value into the register block. (For example: If A[4:0] = `00000' then the PME_STS register will be accessed). Table 10.55 - CR30 RUNTIME REGISTERS BLOCK BASE ADDRESS TYPE: R/W DEFAULT: 0x00 on VCC POR BIT NAME DESCRIPTION Reserved ADR5 ADR6 ADR7 The bits in this register are used to program the location of the Runtime Register Block Base Address. ADR8 ADR9 ADR10 ADR11 BIT NO. 0 1 2 3 4 5 6 7 Rev. 0.5 (03-24-05) Page 194 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet 10.4.49 CR31 CR31 can only be accessed in the configuration state and after the CSR has been initialized to 31H. CR31 is GPIO Direction Register 1 and is used to select the direction of GP11-GP13 and GP16-GP17 pins. Table 10.56 - CR31 TYPE: R/W BIT NAME Reserved GP11 GP12 GP13 Reserved Reserved GP16 GP17 GPIO DIRECTION REGISTER 1 DEFAULT: 0x00 on VTR POR DESCRIPTION The bits in this register are used to select the direction of the GP11-GP13 and GP16-GP17 pins. 0=Input 1=Output BIT NO. 0 1 2 3 4 5 6 7 10.4.50 CR32 CR32 can only be accessed in the configuration state and after the CSR has been initialized to 32H. CR32 is GPIO Polarity Register 1 and is used to select the polarity of GP11-GP13 and GP16-GP17 pins. SMSC SIO10N268 Page 195 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet Table 10.57 - CR32 GPIO POLARITY REGISTER 1 TYPE: R/W DEFAULT: 0x00 on VTR POR BIT NAME DESCRIPTION The bits in this register are used to select the polarity of the GP11Reserved GP13 and GP16-GP17 pins. GP11 GP12 0=Non-Inverted GP13 1=Inverted Reserved Reserved GP16 GP17 BIT NO. 0 1 2 3 4 5 6 7 10.4.51 CR33 CR33 can only be accessed in the configuration state and after the CSR has been initialized to 33H. CR33 is GPIO Direction Register 2. It is used to select the direction of GP20-GP23 pins. Table 10.58 - CR33 TYPE: R/W BIT NAME GP20 GP21 GP22 GP23 Reserved Reserved Reserved Reserved GPIO DIRECTION REGISTER 2 DEFAULT: 0x00 on VTR POR DESCRIPTION These bits are used to select the direction of the GP20-GP23. 0=Input 1=Output Read Only. Read Only. Read Only. Read Only. A read returns 0. A read returns 0. A read returns 0. A read returns 0. BIT NO. 0 1 2 3 4 5 6 7 10.4.52 CR34 CR35 can only be accessed in the configuration state and after the CSR has been initialized to 34H. CR35 is GPIO Polarity Register 2. It is used to select the polarity of GP20-GP23 and IO_PME pins. Table 10.59 - CR34 TYPE: R/W BIT NAME GP20 GP21 GP22 GP23 Reserved GPIO POLARITY REGISTER 2 DEFAULT: 0x00 on VTR POR DESCRIPTION These bits are used to select the polarity of the GP20-GP23 pins. 0=Non-Inverted 1=Inverted Read Only. A read returns 0. BIT NO. 0 1 2 3 4 Rev. 0.5 (03-24-05) Page 196 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet BIT NO. 5 TYPE: R/W BIT NAME IO_PME# Polarity select GPIO POLARITY REGISTER 2 DEFAULT: 0x00 on VTR POR DESCRIPTION This bit is used to select the polarity of the IO_PME# pin. 0=Non-Inverted 1=Inverted Note: configuring this pin function with non-inverted polarity will give an active low output signal. The output type can be either open drain or push-pull. (See CR39). Read Only. A read returns 0. Read Only. A read returns 0. 6 7 Reserved Reserved 10.4.53 CR35 CR35 can only be accessed in the configuration state and after the CSR has been initialized to 35H. CR35 is GPIO Direction Register 3 and is used to select the direction of GP30-GP37 pins. Table 10.60 - CR35 TYPE: R/W BIT NAME GP30 GP31 GP32 GP33 GP34 GP35 GP36 GP37 GPIO DIRECTION REGISTER 3 DEFAULT: 0x00 on VTR POR DESCRIPTION The bits in this register are used to select the direction of the GP30-GP37 pins. 0=Input 1=Output BIT NO. 0 1 2 3 4 5 6 7 10.4.54 CR36 CR36 can only be accessed in the configuration state and after the CSR has been initialized to 36H. CR36 is GPIO Polarity Register 3 and is used to select the polarity of GP30-GP37 pins. SMSC SIO10N268 Page 197 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet Table 10.61 - CR36 TYPE: R/W BIT NAME GP30 GP31 GP32 GP33 GP34 GP35 GP36 GP37 GPIO POLARITY REGISTER 3 DEFAULT: 0x00 on VTR POR DESCRIPTION The bits in this register are used to select the polarity of the GP30GP37 pins. 0=Non-Inverted 1=Inverted BIT NO. 0 1 2 3 4 5 6 7 10.4.55 CR37 CR37 can only be accessed in the configuration state and after the CSR has been initialized to 37H. CR37 is GPIO Direction Register 4 and is used to select the direction of GP40-GP47 pins. Table 10.62 - CR37 TYPE: R/W BIT NAME GP40 GP41 GP42 GP43 GP44 GP45 GP46 GP47 GPIO DIRECTION REGISTER 4 DEFAULT: 0x00 on VTR POR DESCRIPTION The bits in this register are used to select the direction of the GP40-GP47 pins. 0=Input 1=Output BIT NO. 0 1 2 3 4 5 6 7 10.4.56 CR38 CR38 can only be accessed in the configuration state and after the CSR has been initialized to 38H. CR38 is GPIO Polarity Register 4 and is used to select the polarity of GP40-GP47 pins. Table 10.63 - CR38 TYPE: R/W BIT NAME GP40 GP41 GP42 GP43 GP44 GP45 GP46 GP47 GPIO POLARITY REGISTER 4 DEFAULT: 0x00 on VTR POR DESCRIPTION The bits in this register are used to select the polarity of the GP40GP47 pins. 0=Non-Inverted 1=Inverted BIT NO. 0 1 2 3 4 5 6 7 Rev. 0.5 (03-24-05) Page 198 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet 10.4.57 CR39 CR39 can only be accessed in the configuration state and after the CSR has been initialized to 39H. CR39 is GPIO Output Register and is used to select the output buffer of GP11-GP13 and GP16-GP17 pins. Table 10.64 - CR39 TYPE: R/W BIT NAME Reserved GP11 GP12 GP13 Reserved Reserved GP16 GP17 GPIO OUTPUT TYPE REGISTER 1 DEFAULT: 0x00 on VTR POR DESCRIPTION The bits in this register are used to select the output buffer type of the GP11-GP13 and GP16-GP17 pins. 0=Push-pull 1=Open Drain BIT NO. 0 1 2 3 4 5 6 7 Note 10.26 When the GP11/DRVDEN1/FDC_PP pin is set for alternate function DRVDEN1 the output type will be determined by bit[0] of CR05. 10.4.58 CR3A CR3A can only be accessed in the configuration state and after the CSR has been initialized to 3AH. CR3A is a test control register and all bits must be treated as Reserved. NOTE: All test modes are reserved for SMSC use. Activating test mode registers may produce undesired results. Table 10.65 - CR3A TEST 5 BIT NO. 0 1 2 3 4 5 6 7 TYPE: R/W BIT NAME Test 32 Test 33 Test 34 Test 35 Test 36 Test 37 Test 38 Test 39 DEFAULT: 0x00 on VCC POR DESCRIPTION RESERVED FOR SMSC USE 10.4.59 CR3B - CR3F CR3A - CR3F registers are reserved. Reserved registers cannot be written and return 0 when read. The default value of these registers after power up is 00H on VCC POR. SMSC SIO10N268 Page 199 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet 10.4.60 CR40 CR40 can only be accessed in the configuration state and after the CSR has been initialized to 40H. CR40 is GPIO Output Register and is used to select the output buffer for the GP20, GP21, GP23, and IO_PME# pins. Table 10.66 - CR40 GPIO/MISC OUTPUT TYPE REGISTER 2 TYPE: R/W DEFAULT: 0x80 on VTR POR BIT NAME DESCRIPTION GP20 The bits in this register are used to select the output buffer type of the GP20, GP21, GP23, and IO_PME# pins. GP21 Reserved 0=Push-pull GP23 1=Open Drain Reserved Reserved Reserved IO_PME# BIT NO. 0 1 2 3 4 5 6 7 10.4.61 CR41 CR41can only be accessed in the configuration state and after the CSR has been initialized to 41H. CR41is GPIO Output Register and is used to select the output buffer of GP50 to GP57 pins. Table 10.67 - CR41 TYPE: R/W BIT NAME GP50 GP51 GP52 GP53 GP54 GP55 GP56 GP57 GPIO OUTPUT TYPE REGISTER 5 DEFAULT: 0x00 on VTR POR DESCRIPTION The bits in this register are used to select the output buffer type of GP50 to GP57 pins. 0=Push-pull 1=Open Drain BIT NO. 0 1 2 3 4 5 6 7 Rev. 0.5 (03-24-05) Page 200 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet 10.4.62 CR42 CR42 can only be accessed in the configuration state and after the CSR has been initialized to 42H. CR42 is GPIO Direction Register 5 and is used to select the direction of GP50-GP57 pins. Table 10.68 - CR42 TYPE: R/W BIT NAME GP50 GP51 GP52 GP53 GP54 GP55 GP56 GP57 GPIO DIRECTION REGISTER 5 DEFAULT: 0x00 on VTR POR DESCRIPTION The bits in this register are used to select the direction of the GP50GP57 pins. 0=Input 1=Output BIT NO. 0 1 2 3 4 5 6 7 10.4.63 CR43 CR43 can only be accessed in the configuration state and after the CSR has been initialized to 43H. CR43 is GPIO Polarity Register 5 and is used to select the polarity of GP50-GP57 pins. Table 10.69 - CR43 TYPE: R/W BIT NAME GP50 GP51 GP52 GP53 GP54 GP55 GP56 GP57 GPIO POLARITY REGISTER 5 DEFAULT: 0x00 on VTR POR DESCRIPTION The bits in this register are used to select the polarity of the GP50GP57 pins. 0=Non-Inverted 1=Inverted BIT NO. 0 1 2 3 4 5 6 7 SMSC SIO10N268 Page 201 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet 10.4.64 CR44 CR44 can only be accessed in the configuration state and after the CSR has been initialized to 44H. The bits in this register are used to select an alternate function of GP11-GP13 pins. Table 10.70 - CR44 GPIO ALTERNATE FUNCTION SELECT REGISTER 1 TYPE: R/W DEFAULT: 0x00 on VTR POR BIT NAME DESCRIPTION Reserved Reads return 0. GP11 Alternate Function Select bit[3] bit[2] Function 0 0 GPIO (default) 0 1 DRVDEN1 1 0 FDC_PP (Note) 1 1 Reserved See Note 10.27 below. Alternate Function Select bit[5] bit[4] Function 0 0 GPIO (default) 0 1 IO_SMI# (Note) 1 0 Reserved 1 1 Reserved See Note 10.28 below. Alternate Function Select bit[7] bit[6] Function 0 0 GPIO (default) 0 1 IRQIN1 (Note) 1 0 LED1 1 1 Reserved See Note 10.29 below. BIT NO. 0,1 2,3 4,5 GP12 6,7 GP13 NOTE: If the Alternate Function is selected, the corresponding bits in the "GPIO Direction Registers" and "GPIO Polarity Registers" must be configured accordingly. Note 10.27 When the FDC_PP function is selected, the pin must be selected as an input. Polarity is controlled by the polarity bit. If enabled for PME or SMI, the interrupt is generated on either edge. Note 10.28 Selecting the IO_SMI# function with GP12 configured with non-inverted polarity will give an active low output signal. The output type can be programmed for open drain via CR39. Note 10.29 See Application Note in section 8.14.2 Routable IRQ Inputs. Rev. 0.5 (03-24-05) Page 202 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet 10.4.65 CR45 CR45 can only be accessed in the configuration state and after the CSR has been initialized to 45H. The bits in this register are used to select an alternate function of GP16-GP17 pins. Table 10.71 - CR45 GPIO ALTERNATE FUNCTION SELECT REGISTER 2 TYPE: R/W DEFAULT: 0x50 on VTR POR, BITS[7:4] VTR POR, VCC POR, and Hard Reset BIT NAME DESCRIPTION Reserved Reads return 0. Reserved Reads return 0. GP16 Alternate Function Select bit[5] bit[4] Function 0 0 GPIO 0 1 XA20 (default) - Note 1 0 Reserved 1 1 Reserved See Note 10.30 below. Alternate Function Select bit[7] bit[6] Function 0 0 GPIO 0 1 XA19 (default) - Note 1 0 Reserved 1 1 Reserved See Note 10.31 below. BIT NO. 0,1 2,3 4,5 6,7 GP17 NOTE: If the Alternate Function is selected, the corresponding bits in the "GPIO Direction Registers" and "GPIO Polarity Registers" must be configured accordingly. Note 10.30 Bits[4:5] are reset on VTR POR, VCC POR, and Hard Reset. Note 10.31 Bits[7:6] are reset on VTR, VCC, and Hard Reset. SMSC SIO10N268 Page 203 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet 10.4.66 CR46 CR46 can only be accessed in the configuration state and after the CSR has been initialized to 46H. The bits in this register are used to select an alternate function of GP20-GP23 pins. Table 10.72 - CR46 GPIO ALTERNATE FUNCTION SELECT REGISTER 3 TYPE: R/W DEFAULT: 0x00 on VTR POR BIT NAME DESCRIPTION GP20 Alternate Function Select bit[1] bit[0] Function 0 0 GPIO (default) 0 1 IRRX2 1 0 IRQIN3 1 1 Reserved GP21 Alternate Function Select bit[3] bit[2] Function 0 0 GPIO (default) 0 1 IRTX2 1 0 WDT 1 1 Reserved GP22 Alternate Function Select bit[5] bit[4] Function 0 0 GPIO (default) 0 1 HPMODE (Note) 1 0 nXCS2 1 1 Reserved See Note 10.32 below. Alternate Function Select bit[7] bit[6] Function 0 0 GPIO (default) 0 1 LED2 1 0 IRQIN2 (Note) 1 1 Reserved BIT NO. 0,1 2,3 4,5 6,7 GP23 NOTE: If the Alternate Function is selected, the corresponding bits in the "GPIO Direction Registers" and "GPIO Polarity Registers" must be configured accordingly. Note 10.32 HPMODE is programmable in the IRQIN1/HPMODE/SIRQ_CLKRUN_En Configuration Register at offset CR29. The default HPMODE is the IRMODE function. Note 10.33 See Application Note in section 8.14.2 Routable IRQ Inputs. Rev. 0.5 (03-24-05) Page 204 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet 10.4.67 CR48 CR48 can only be accessed in the configuration state and after the CSR has been initialized to 48H. The bits in this register are used to select an alternate function of GP30-GP33 pins. Table 10.73 - CR48 GPIO ALTERNATE FUNCTION SELECT REGISTER 5 TYPE: R/W DEFAULT: 0x00 on VTR POR BIT NAME DESCRIPTION GP30 Alternate Function Select bit[1] bit[0] Function 0 0 GPIO (default) 0 1 nRI3 1 0 Reserved 1 1 Reserved GP31 Alternate Function Select bit[3] bit[2] Function 0 0 GPIO (default) 0 1 nDCD3 1 0 Reserved 1 1 Reserved GP32 Alternate Function Select bit[5] bit[4] Function 0 0 GPIO (default) 0 1 nRXD3 1 0 Reserved 1 1 Reserved GP33 Alternate Function Select bit[7] bit[6] Function 0 0 GPIO (default) 0 1 nTXD3 1 0 Reserved 1 1 Reserved BIT NO. 0,1 2,3 4,5 6,7 NOTE: If the Alternate Function is selected, the corresponding bits in the "GPIO Direction Registers" and "GPIO Polarity Registers" must be configured accordingly. 10.4.68 CR49 CR49 can only be accessed in the configuration state and after the CSR has been initialized to 49H. The bits in this register are used to select an alternate function of GP34-GP37 pins. SMSC SIO10N268 Page 205 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet Table 10.74 - CR49 GPIO ALTERNATE FUNCTION SELECT REGISTER 6 TYPE: R/W DEFAULT: 0x00 on VTR POR BIT NAME DESCRIPTION GP34 Alternate Function Select bit[1] bit[0] Function 0 0 GPIO (default) 0 1 nDSR3 1 0 Reserved 1 1 Reserved GP35 Alternate Function Select bit[3] bit[2] Function 0 0 GPIO (default) 0 1 nRTS3 1 0 Reserved 1 1 Reserved GP36 Alternate Function Select bit[5] bit[4] Function 0 0 GPIO (default) 0 1 nCTS3 1 0 Reserved 1 1 Reserved GP37 Alternate Function Select bit[7] bit[6] Function 0 0 GPIO (default) 0 1 nDTR3 1 0 Reserved 1 1 Reserved BIT NO. 0,1 2,3 4,5 6,7 NOTE: If the Alternate Function is selected, the corresponding bits in the "GPIO Direction Registers" and "GPIO Polarity Registers" must be configured accordingly. 10.4.69 CR4A CR4A can only be accessed in the configuration state and after the CSR has been initialized to 4AH. The bits in this register are used to select an alternate function of GP40-GP43 pins. Table 10.75 - CR4A GPIO ALTERNATE FUNCTION SELECT REGISTER 7 TYPE: R/W DEFAULT: 0x00 on VTR POR BIT NAME DESCRIPTION GP40 Alternate Function Select bit[1] bit[0] Function 0 0 GPIO (default) 0 1 nRI4 1 0 Reserved 1 1 Reserved BIT NO. 0,1 Rev. 0.5 (03-24-05) Page 206 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet BIT NO. 2,3 4,5 6,7 GPIO ALTERNATE FUNCTION SELECT REGISTER 7 TYPE: R/W DEFAULT: 0x00 on VTR POR BIT NAME DESCRIPTION GP41 Alternate Function Select bit[3] bit[2] Function 0 0 GPIO (default) 0 1 nDCD4 1 0 Reserved 1 1 Reserved GP42 Alternate Function Select bit[5] bit[4] Function 0 0 GPIO (default) 0 1 nRXD4 1 0 Reserved 1 1 Reserved GP43 Alternate Function Select bit[7] bit[6] Function 0 0 GPIO (default) 0 1 nTXD4 1 0 Reserved 1 1 Reserved NOTE: If the Alternate Function is selected, the corresponding bits in the "GPIO Direction Registers" and "GPIO Polarity Registers" must be configured accordingly. 10.4.70 CR4B CR4B can only be accessed in the configuration state and after the CSR has been initialized to 4BH. The bits in this register are used to select an alternate function of GP44-GP47 pins. Table 10.76 - CR4B GPIO ALTERNATE FUNCTION SELECT REGISTER 8 TYPE: R/W DEFAULT: 0x00 on VTR POR BIT NAME DESCRIPTION GP44 Alternate Function Select bit[1] bit[0] Function 0 0 GPIO (default) 0 1 nDSR4 1 0 Reserved 1 1 Reserved GP45 Alternate Function Select bit[3] bit[2] Function 0 0 GPIO (default) 0 1 nRTS4 1 0 Reserved 1 1 Reserved BIT NO. 0,1 2,3 SMSC SIO10N268 Page 207 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet BIT NO. 4,5 6,7 GPIO ALTERNATE FUNCTION SELECT REGISTER 8 TYPE: R/W DEFAULT: 0x00 on VTR POR BIT NAME DESCRIPTION GP46 Alternate Function Select bit[5] bit[4] Function 0 0 GPIO (default) 0 1 nCTS4 1 0 Reserved 1 1 Reserved GP47 Alternate Function Select bit[7] bit[6] Function 0 0 GPIO (default) 0 1 nDTR4 1 0 Reserved 1 1 Reserved NOTE: If the Alternate Function is selected, the corresponding bits in the "GPIO Direction Registers" and "GPIO Polarity Registers" must be configured accordingly. 10.4.71 CR4C CR4C can only be accessed in the configuration state and after the CSR has been initialized to 4CH. The bits in this register are used to select an alternate function of GP50-GP53 pins. Table 10.77 - CR4C GPIO ALTERNATE FUNCTION SELECT REGISTER 9 TYPE: R/W DEFAULT: 0x00 on VTR POR BIT NAME DESCRIPTION GP50 Alternate Function Select bit[1] bit[0] Function 0 0 GPIO (default) 0 1 nRI2 1 0 Reserved 1 1 Reserved GP51 Alternate Function Select bit[3] bit[2] Function 0 0 GPIO (default) 0 1 nDCD2 1 0 Reserved 1 1 Reserved GP52 Alternate Function Select bit[5] bit[4] Function 0 0 GPIO (default) 0 1 RXD2/IRRX 1 0 Reserved 1 1 Reserved BIT NO. 0,1 2,3 4,5 Rev. 0.5 (03-24-05) Page 208 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet BIT NO. 6,7 GPIO ALTERNATE FUNCTION SELECT REGISTER 9 TYPE: R/W DEFAULT: 0x00 on VTR POR BIT NAME DESCRIPTION GP53 Alternate Function Select bit[7] bit[6] Function 0 0 GPIO (default) 0 1 TXD2/IRTX 1 0 Reserved 1 1 Reserved NOTE: If the Alternate Function is selected, the corresponding bits in the "GPIO Direction Registers" and "GPIO Polarity Registers" must be configured accordingly. 10.4.72 CR4D CR4D can only be accessed in the configuration state and after the CSR has been initialized to 4DH. The bits in this register are used to select an alternate function of GP54-GP57 pins. Table 10.78 - CR4D GPIO ALTERNATE FUNCTION SELECT REGISTER 10 TYPE: R/W DEFAULT: 0x00 on VTR POR BIT NAME DESCRIPTION GP54 Alternate Function Select bit[1] bit[0] Function 0 0 GPIO (default) 0 1 nDSR2 1 0 Reserved 1 1 Reserved GP55 Alternate Function Select bit[3] bit[2] Function 0 0 GPIO (default) 0 1 nRTS2 1 0 Reserved 1 1 Reserved GP56 Alternate Function Select bit[5] bit[4] Function 0 0 GPIO (default) 0 1 nCTS2 1 0 Reserved 1 1 Reserved GP57 Alternate Function Select bit[7] bit[6] Function 0 0 GPIO (default) 0 1 nDTR2 1 0 Reserved 1 1 Reserved BIT NO. 0,1 2,3 4,5 6,7 NOTE: If the Alternate Function is selected, the corresponding bits in the "GPIO Direction Registers" and "GPIO Polarity Registers" must be configured accordingly. SMSC SIO10N268 Page 209 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet 10.4.73 CR4E CR4E can only be accessed in the configuration state and after the CSR has been initialized to 4EH. Table 10.79 - CR4E X-BUS BASE I/O ADDRESS FOR CHIP SELECT 1 - HIGH BYTE DEFAULT: 0x00 on VCC POR and Hard Reset TYPE: R/W when CR4F Bit[1] = 0 Read-Only when CR4F Bit[1] = 1 BIT NO. BIT NAME DESCRIPTION 0-3 Base Address CR4E sets the high byte of the base I/O address for chip select 1. High Byte Bits [3:0] =address[11:8] Note: Bits[15:12] must be `0' since the chip performs 16-bit address qualification on the base I/O addresses. 4-7 Reserved Reads return 0. 10.4.74 CR4F CR4F can only be accessed in the configuration state and after the CSR has been initialized to 4FH. Table 10.80 - CR4F X-BUS BASE ADDRESS FOR CHIP SELECT 1 - LOW BYTE DEFAULT: 0x01 on VCC POR and Hard Reset TYPE: R/W when CR4F Bit[1] = 0 Read-Only when CR4F Bit[1] = 1 BIT NO. BIT NAME DESCRIPTION 0 Disable bit Bit[0] = Disable bit for nXCS1. 0=enable chip select 1=disable chip select (default) 1 Write Protect Bit 1 is the write protect bit for registers CR4E and CR4F. Bit[1] = Register CR4E, CR4F Write Protect. Cleared by VCC POR and Hard Reset only. Cannot be cleared by software writing to this bit. 0=Register CR4E and CR4F are read/write 1=Register CR4E and CR4F are read-only CR4F sets the Low byte of the base I/O address for chip select 1. Bits [7:2] are X-Bus mode dependent as follows: Mode 1: Bits [7:2] = address[7:2] Mode 2: Bits [7:4] = address[7:4] Bits [3:2] = These bits are R/W. They are not used in the address decode. Mode 3: Bits [7:3] = address[7:3] Bit [2] = address[1] Note: Bit [0] must be 0 for mode 3. 2-7 Base Address Low Byte Rev. 0.5 (03-24-05) Page 210 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet 10.4.75 CR50 CR50 can only be accessed in the configuration state and after the CSR has been initialized to 50H. Table 10.81 - CR50 X-BUS BASE ADDRESS FOR CHIP SELECT 2 - HIGH BYTE DEFAULT: 0x00 on VCC POR and Hard Reset TYPE: R/W when CR50 Bit[1] = 0 Read-Only when CR51 Bit[1] = 1 BIT NO. BIT NAME DESCRIPTION 0-3 Base Address CR50 sets the high byte of the base I/O address for chip select 2. High Byte Bits [3:0] = address[11:8] Note: Bits[15:12] must be `0' since the chip performs 16-bit address qualification on the base I/O addresses. 4-7 Reserved Reads return 0. 10.4.76 CR51 CR51 can only be accessed in the configuration state and after the CSR has been initialized to 51H. Table 10.82 - CR51 X-BUS BASE ADDRESS FOR CHIP SELECT 2 - LOW BYTE DEFAULT: 0x01 on VCC POR and Hard Reset TYPE: R/W when CR51 Bit[1] = 0 Read-Only when CR51 Bit[1] = 1 BIT NO. BIT NAME DESCRIPTION 0 Disable bit Bit[0] = Disable bit for nXCS2. 0=enable chip select 1=disable chip select (default) 1 Write Protect Bit [1] is the write protect bit for registers CR50 and CR51. Bit[1] = Register CR50, CR51 Write Protect. Cleared by VCC POR and Hard Reset only. Cannot be cleared by software writing to this bit. 0=Register CR50 and CR51 are read/write 1=Register CR50 and CR51 are read-only CR51 sets the Low byte of the base I/O address for chip select 2. Bits [7:2] are X-Bus mode dependent as follows: Mode 1: Bits [7:2] = address[7:2] Mode 2: Bits [7:4] = address[7:4] Bits [3:2] = These bits are R/W. They are not used in the address decode. Mode 3: Bits [7:3] = address[7:3] Bit [2] = address[1] Note: Bit [0] must be 0 for mode 3. 2-7 Base Address Low Byte SMSC SIO10N268 Page 211 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet 10.4.77 CR52 CR52 can only be accessed in the configuration state and after the CSR has been initialized to 52H. Table 10.83 - CR52 X-BUS I/O SELECT REGISTER DEFAULT: 0x00 on VCC POR and Hard Reset TYPE: R/W when CR52 Bit[7] = 0 Read-Only when CR52 Bit[7] = 1 BIT NO. BIT NAME DESCRIPTION 0-1 X-Bus Mode Bit [1:0] X-Bus Mode. 00=Mode 1 01=Mode 2 10=Mode 3 11=Reserved Note that the GPIOs must be configured properly to use the selected mode. The GPIOs are not automatically configured for the mode selected. 2-3 Pulse Width Bits [3:2] X-Bus Read/Write Pulse Width Selection. These bits Selection select the pulse width of the X-bus read and write strobes. They extend the LPC cycle accordingly by adding wait states (sync fields) into the cycle. 11=540nsec min 10=420nsec min 01=300nsec min 00=180nsec min (default) 4-6 Reserved Reads return 0. 7 Register Write Bit [7] Register Write Protect. Cleared by VCC POR and Hard Protect Reset only. Cannot be cleared by software writing this bit. 0=X-Bus selection register is Read/Write. 1=X-Bus Selection register is Read-Only 10.4.78 CR53 CR53 can only be accessed in the configuration state and after the CSR has been initialized to 53H. Table 10.84 - CR53 X-BUS CHIP SELECT 0 REGISTER DEFAULT: 0x8C on VCC POR and Hard Reset TYPE: R/W when CR53 Bit[0] = 0 Read-Only when CR53 Bit[0] = 1 BIT NO. BIT NAME DESCRIPTION 0 Write Protect Bits [0] = Write Protect for Chip Select 0 register (Note: Software cannot clear this bit.) 0=Register CR53 is read/write 1=Register CR53 is read-only 1 Reserved Reads return 0. Rev. 0.5 (03-24-05) Page 212 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet X-BUS CHIP SELECT 0 REGISTER DEFAULT: 0x8C on VCC POR and Hard Reset TYPE: R/W when CR53 Bit[0] = 0 Read-Only when CR53 Bit[0] = 1 BIT NO. BIT NAME DESCRIPTION 2-3 Pulse Width Bits[3:2] X-Bus Read/Write Pulse Width Selection. These bits Selection select the pulse width of the X-bus memory read and write strobes. They extend the LPC cycle accordingly by adding wait states (sync fields) into the cycle. 11=150nsec min (default) 10=120nsec min 01=90nsec min 00=60nsec min 4-6 Reserved Reads return 0. 7 Enable Bit [7] Enable for Chip Select 0 0=disable chip select 1=enable chip select 10.4.79 CR54 CR54 can only be accessed in the configuration state and after the CSR has been initialized to 54H. Table 10.85 - CR54 FWH ID SELECT TYPE: R/W BIT NO. 0-3 BIT NAME ID Select DEFAULT: 0XX00000b on VCC POR and Hard Reset (Note: X = Strap Options) DESCRIPTION Bits [3:0] ID Select Contains the FWH ID number. See Note 10.34 below. Bit[4] ID SELECT ENABLE 0=All FWH cycles will be claimed by FWH interface. 1=Only FWH cycles that contain ID values that match the value programmed in the ID Select bits will be claimed. All other FWH cycles will be ignored. Bit[5] FWH SELECT 0=LPC cycles are forwarded to X-Bus interface 1=FWH cycles are forwarded to X-Bus interface See Note 10.35 below. Bit[6] MEMORY CYCLES ENABLED 0=Neither LPC memory or FWH cycles will be decoded for the XBus interface. 1=LPC memory cycles or FWH cycles will be decoded for the XBus interface depending on the status of the FWHSEL bit Read Only. A read returns 0 4 IDSELEN 5 FWHSEL 6 MEMEN 7 Reserved Note 10.34 If IDSELEN is asserted bits[3:0] are compared with the FWH ID and must match for the FWH cycle to be claimed. SMSC SIO10N268 Page 213 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet Note 10.35 LPC and FWH cycles are only forwarded to X-Bus interface when the MEMEN bit is asserted `1'. FWHSEL can be set by a strap option. Note 10.36 MEMEN can be set by a strap option. Rev. 0.5 (03-24-05) Page 214 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet 10.5 Logical Device Base I/O Address and Range Table 10.86 - I/O Base Address Configuration Register Description LOGICAL DEVICE FDC REGISTER INDEX 0x20 BASE I/O RANGE (Note 10.37) [0x0100:0x03F0] on 16-byte boundaries FIXED BASE OFFSETS +0 : SRA +1 : SRB +2 : DOR +3 : TDR +4 : MSR/DSR +5 : FIFO +7 : DIR/CCR Parallel Port 0x23 [0x0100:0x03FC] on 4-byte boundaries (EPP Not supported) or [0x0100:0x03F8] on 8-byte boundaries (all modes supported, EPP is only available when the base address is on an 8-byte boundary) [0x0100:0x03F8] on 8 byte boundaries +0 : Data/ecpAfifo +1 : Status +2 : Control +400h : cfifo/ecpDfifo/tfifo/cnfgA +401h : cnfgB +402h : ecr +3 : EPP Address +4 : EPP Data 0 +5 : EPP Data 1 +6 : EPP Data 2 +7 : EPP Data 3 +0 : RB/TB/LSB div +1 : IER/MSB div +2 : IIR/FCR +3 : LCR +4 : MCR +5 : LSR +6 : MSR Serial Port 1 0x24 +7 : SCR Serial Port 2 0x25 [0x0100:0x03F8] on 8-byte boundaries +0 : RB/TB/LSB div +1 : IER/MSB div +2 : IIR/FCR +3 : LCR +4 : MCR +5 : LSR +6 : MSR +7 : SCR 0x2B (FIR/CIR) [0x100:0x07F8] on 8-byte boundaries +0 : DR/SCEA/CIRC/IDH/(IRDACR/BOFH) +1 : INTID/SCEB/CIRCR/IDL/BOFL +2 : IER/FIFOT/CIRBR/CID/BWCL +3 : LSR/LSA/VERN/(BWCH/TDSH) +4 : LCA/(IRQL/DMAC)/TDSL +5 : LCB/RDSH +6 : BS/RDSL +7 : MCR SMSC SIO10N268 Page 215 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet LOGICAL DEVICE Runtime Register Block REGISTER INDEX 0x30 BASE I/O RANGE (Note 10.37) [0x0100:0x0FE0] on 32-byte boundaries FIXED BASE OFFSETS +00 : PME_STS . . . +1B : PME_EN4 (See Table 9.1 in Chapter 9 Runtime Registers for Full List) See Configuration Registers in section 10.3 Configuration Registers Summary on page 165. They are accessed through the index and DATA ports located at the Configuration Port address and the Configuration Port address +1 respectively. +0 : RB/TB/LSB div +1 : IER/MSB div +2 : IIR/FCR +3 : LCR +4 : MCR +5 : LSR +6 : MSR Config. Port 0x12, 0x13 (Note 2) [0x0100:0x07FE] On 2-byte boundaries Serial Port 3 0x1B [0x0100:0x03F8] on 8 byte boundaries +7 : SCR Serial Port 4 0x1C [0x0100:0x03F8] on 8 byte boundaries +0 : RB/TB/LSB div +1 : IER/MSB div +2 : IIR/FCR +3 : LCR +4 : MCR +5 : LSR +6 : MSR +7 : SCR +0: X-bus CS1 Address X-Bus 0x4E, 0x4F 0x50, 0x51 Mode 1: [0x0000:0x0FFC] ON 4 BYTE BOUNDARIES Mode 2: [0x0000:0x0FF0] ON 16 BYTE BOUNDARIES Mode 3: [0x0000:0xFFE] ON 2 BYTE BOUNDARIES Mode 1: +0: X-bus CS2 Address [0x0000:0x0FFC] ON 4 BYTE BOUNDARIES Mode 2: [0x0000:0x0FF0] ON 16 BYTE BOUNDARIES Mode 3: [0x0000:0xFFE] ON 2 BYTE BOUNDARIES Rev. 0.5 (03-24-05) Page 216 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet Note 10.37 The Configuration Port is at either 0x02E or 0x04E (for SYSOPT=0 or SYSOPT=1) at power up and can be relocated via CR12 and CR13. 10.6 Note A. Logical Device IRQ and DMA Operation 1) IRQ and DMA Enable and Disable: Any time the IRQ or DMA channel for a logical block is disabled by a register bit in that logical block, the IRQ and/or DMA channel is disabled. This is in addition to the IRQ and DMA channel disabled by the Configuration Registers (active bit or address not valid). a) FDC: For the following cases, the IRQ and DMA channel used by the FDC are disabled. Digital Output Register (Base+2) bit D3 (DMAEN) set to "0". The FDC is in power down (disabled). b) Serial Ports: Modem Control Register (MCR) Bit D2 (OUT2) - When OUT2 is a logic "0", the serial port interrupts disabled. Disabling DMA Enable bit, disables DMA for UART2. Refer to the IrCC specification. c) Parallel Port: i. SPP and EPP modes: Control Port (Base+2) bit D4 (IRQE) set to "0", IRQ is disabled. ii. ECP Mode: 1) (DMA) dmaEn from ecr register. See Table 10.87 below. 2) IRQ - See Table 10.87 below. Table 10.87 - IRQ & DMA Operation in ECP Mode MODE (FROM ECR REGISTER) 000 PRINTER 001 SPP 010 FIFO 011 ECP 100 EPP 101 RES 110 TEST 111 CONFIG IRQ CONTROLLED BY IRQE IRQE (on) (on) IRQE IRQE (on) IRQE DMA CONTROLLED BY dmaEn dmaEn dmaEn dmaEn dmaEn dmaEn dmaEn dmaEn SMSC SIO10N268 Page 217 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet Chapter 11 Operational Description 11.1 Maximum Guaranteed Ratings o o Operating Temperature Range........................................................................................................................... 0 C to +70 C o Storage Temperature Range ............................................................................................................................-55 to +150oC Lead Temperature Range..................................................................................................Refer to JEDEC Spec. J-STD-020 Positive Voltage on any pin, with respect to Ground ................................................................................................VCC+0.3V Negative Voltage on any pin, with respect to Ground......................................................................................................-0.3V Maximum VCC ..................................................................................................................................................................+5.5V NOTE: Stresses above those listed above could cause permanent damage to the device. This is a stress rating only and functional operation of the device at any other condition above those indicated in the operation sections of this specification is not implied. When powering this device from laboratory or system power supplies, it is important that the Absolute Maximum Ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes on their outputs when the AC power is switched on or off. In addition, voltage transients on the AC power line may appear on the DC output. If this possibility exists, it is suggested that a clamp circuit be used. NOTE: 11.2 DC Electrical Characteristics MIN TYP MAX UNITS COMMENTS (TA = 00C - 700C, VCC = +3.3 V 10%) PARAMETER SYMBOL I Type Input Buffer Low Input Level High Input Level IS Type Input Buffer Low Input Level High Input Level Schmitt Trigger Hysteresis IPD Type Input Buffer Low Input Level High Input Level Internal Pulldown VILI VIHI 0.8 2.0 V V TTL Levels VILIS VIHIS VHYS 2.2 100 0.8 V V mV Schmitt Trigger Schmitt Trigger VILIPD VIHIPD 2.0 30 0.8 V V A TTL Levels Rev. 0.5 (03-24-05) Page 218 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet PARAMETER Input Leakage, I and IS Buffers Low Input Leakage High Input Leakage SYMBOL MIN TYP MAX UNITS COMMENTS IIL IIH -10 -10 +10 +10 A A VIN = 0 VIN = VCC O6 Type Buffer Low Output Level High Output Level VOL VOH 2.4 0.4 V V IOL = 6mA IOH = -3mA IO8 Type Buffer Low Output Level High Output Level Leakage Current VOL VOH ILEAK 2.4 10 0.4 V V A IOL = 8mA IOH = -4mA VIN = 0 to VCC (Note 11.1) O8 Type Buffer Low Output Level High Output Level VOL VOH 2.4 0.4 V V IOL = 8mA IOH = -4mA OD8 Type Buffer Low Output Level Leakage Current O12 Type Buffer Low Output Level High Output Level VOL ILEAK 0.4 +10 V A IOL = 8mA VIN = 0 to VCC VOL VOH 2.4 0.4 V V IOL = 12mA IOH = -6mA IO12 Type Buffer Low Output Level High Output Level Leakage Current VOL VOH ILEAK 2.4 10 0.4 V V A IOL = 12mA IOH = -6mA VIN = 0 to VCC (Note 11.1) SMSC SIO10N268 Page 219 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet PARAMETER OD12 Type Buffer Low Output Level Leakage Current OD14 Type Buffer Low Output Level Leakage Current OP14 Type Buffer Low Output Level High Output Level Leakage Current SYMBOL MIN TYP MAX UNITS COMMENTS VOL ILEAK 0.4 +10 V A IOL = 12mA VIN = 0 to VCC VOL ILEAK 0.4 +10 V A IOL = 14mA VIN = 0 to VCC VOL VOH ILEAK 2.4 0.4 V V IOL = 14mA IOH = -14mA VIN = 0 to VCC (Note 11.1) +10 A IOP14 Type Buffer Low Output Level High Output Level Leakage Current VOL VOH ILEAK IIL 2.4 10 10 0.4 V V A A IOL = 14mA IOH = -14mA VIN = 0 to VCC (Note 11.1) VCC = 0V VIN = 5.5V Max Backdrive Protect/ChiProtect (All pins excluding LAD[3:0], LDRQ#, LPCPD#, LFRAME#) 5V Tolerant Pins (All pins excluding LAD[3:0], LDRQ#, LPCPD#, LFRAME#) Inputs and Outputs in High Impedance State LPC Bus Pins (LAD[3:0], LDRQ#, LPCPD#, LFRAME#) VCC Supply Current Active IIL 10 A VCC = 3.3V VIN = 5.5V Max IIL 10 A ICC 17 (Note 11.2) mA Trickle Supply Voltage VTR VCC min -.5V (Note 11.4) VCC max V VCC = 0V and VCC = 3.3V VIN = 3.6V Max All outputs open, all inputs transitioning from/to 0V to/from 3.3V VCC must not be greater than .5V above VTR All outputs open, all inputs transitioning from/to 0V to/from 3.3V SMSC SIO10N268 VTR Supply Current Active ITR 0.2 (Note 11.2, Note 11.3) mA Rev. 0.5 (03-24-05) Page 220 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet Note 11.1 Note 11.2 All output leakage's are measured with all pins in high impedance. These values are estimated. They will be updated after characterization. Contact SMSC for the latest values. Max ITR with VCC = 3.3V (nominal) is 0.2mA. Max ITR with VCC = 0V (nominal) is 60A. The minimum value given for VTR applies when VCC is active. When VCC is 0V, the minimum VTR is 0V. Note 11.3 Note 11.4 CAPACITANCE TA = 250C; fc = 1MHz; VCC = 3.3V 10% LIMITS PARAMETER SYMBOL MIN TYP Clock Input Capacitance CIN Input Capacitance CIN Output Capacitance COUT MAX 20 10 20 UNIT pF pF pF TEST CONDITION All pins except pin under test tied to AC ground SMSC SIO10N268 Page 221 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet Chapter 12 Timing Diagrams For the Timing Diagrams shown, the following capacitive loads are used on outputs. NAME SER_IRQ nLAD[3:0] LDRQ# nDIR nSTEP nDS0-1 nWDATA PD[0:7] nSTROBE nALF SLCTIN TXD1 TXD2 CLKRUN# nXCS[0:2] XA[0:20] XD[0:7] nXRD nXWR CAPACITANCE TOTAL (pF) 50 50 50 240 240 240 240 240 240 240 240 50 50 50 50 50 50 50 50 12.1 Power-up Timing t1 V cc t2 t3 A ll H o s t A ccesses Figure 12.1 - Power-Up Timing Rev. 0.5 (03-24-05) Page 222 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet NAME t1 t2 t3 DESCRIPTION Vcc Slew from 2.7V to 0V Vcc Slew from 0V to 2.7V All Host Accesses After Powerup (Note 12.1) MIN 300 100 125 TYP MAX UNITS s s 500 s Note 12.1 Internal write-protection period after Vcc passes 2.7 volts on power-up. 12.2 Input Clock Timing CLOCKI t1 t2 t2 Figure 12.2 - 14MHZ Clock Timing NAME t1 t2 DESCRIPTION Clock Cycle Time for 14.318MHZ Clock High Time/Low Time for 14.318MHz Clock Rise Time/Fall Time (not shown) MIN 20 TYP 69.84 35 MAX 5 UNITS ns ns ns P C I_ C L K t5 t1 t3 t4 t2 Figure 12.3 - PCI Clock Timing NAME t1 t2 t3 t4 t5 DESCRIPTION Period High Time Low Time Rise Time Fall Time MIN 30 12 12 TYP MAX 33.3 3 3 UNITS nsec nsec nsec nsec nsec SMSC SIO10N268 Page 223 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet 12.3 LPC Timing (LPC Mode Only) nPCI_RESET t1 Figure 12.4 - Reset Timing NAME t1 DESCRIPTION PCI_RESET# width MIN 1 TYP MAX UNITS ms CLK t1 Output Delay t2 t3 Tri-State Output Figure 12.5 - Output Timing Measurement Conditions, LPC Signals NAME DESCRIPTION t1 CLK to Signal Valid Delay - Bused Signals t2 Float to Active Delay t3 Active to Float Delay MIN 2 2 TYP MAX 11 11 28 UNITS ns ns ns t1 CLK Input Inputs Valid t2 Figure 12.6 - Input Timing Measurement Conditions, LPC Signals NAME DESCRIPTION t1 Input Set Up Time to CLK - Bused Signals t2 Input Hold Time from CLK MIN 7 0 TYP MAX UNITS ns ns Rev. 0.5 (03-24-05) Page 224 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet PCI_CLK LFRAME# LAD[3:0]# NOTE: L1 L2 Address Data TAR Sync=0110 L3 TAR L1=Start; L2=CYCTYP+DIR; L3=Sync of 0000 Figure 12.7 - I/O Write PCI_CLK LFRAME# LAD[3:0]# NOTE: L1 L2 Address TAR Sync=0110 L3 Data TAR L1=Start; L2=CYCTYP+DIR; L3=Sync of 0000 Figure 12.8 - I/O Read PCI_CLK LDRQ# Start MSB LSB ACT Figure 12.9 - DMA Request Assertion Through LDRQ# PCI_CLK LFRAME# LAD[3:0]# Start C+D CHL Size TAR Sync=0101 L1 Data TAR NOTE: L1=Sync of 0000 Figure 12.10 - DMA Write (First Byte) SMSC SIO10N268 Page 225 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet PCI_CLK LFRAME# LAD[3:0]# Start C+D CHL Size Data TAR Sync=0101 L1 TAR NOTE: L1=Sync of 0000 Figure 12.11 - DMA Read (First Byte) 12.4 X-Bus Timing (LPC Mode Only) 12.4.1 X-Bus I/O Timing NOTE: The following timing values are based on a 33MHz PCI clock. Timing values will vary with variations in the PCI clock frequency. 12.4.1.1 X-Bus I/O Read Timing t3 Ax, nXCSx t1 t2 t5 nXRD t4 Data Valid Figure 12.12 - X-Bus I/O Read Timing NAME t1 t2 DESCRIPTION nXCS active to nXRD active nXRD active to nXRD inactive t3 t4 t5 NOTE: nXRD inactive to nxCS inactive Data valid to nXRD inactive nXRD inactive to data invalid MIN 100 A: 180 B: 300 C: 420 D: 540 40 20 0 TYP MAX 190 UNITS ns ns ns ns ns Cases A-D for t2 correspond to the different pulse width options for the X-Bus read strobe. See the Pulse Width Selection bits located in the X-Bus I/O Select Register at offset CR52. Rev. 0.5 (03-24-05) Page 226 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet 12.4.1.2 X-Bus I/O Write Timing t3 Ax, nXCSx t1 t2 t5 nXWR t4 Data Valid Figure 12.13 - X-Bus Write Timing NAME t1 t2 DESCRIPTION nXCS active to nXWR active nXWR active to nXWR inactive t3 t4 t5 NOTE: nXWR inactive to nXCS inactive Data valid to nXWR active nXWR inactive to data invalid MIN 100 A: 180 B: 300 C: 420 D: 540 40 22 45 TYP MAX 190 UNITS ns ns ns ns ns Cases A-D for t2 correspond to the different pulse width options for the X-Bus write strobe. See the Pulse Width Selection bits located in the X-Bus I/O Select Register at offset CR52. SMSC SIO10N268 Page 227 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet 12.4.2 Representative LPC I/O Cycle to X-Bus Cycle Timing 12.4.2.1 X-Bus I/O Read Cycle: LPC I/O Read Cycle - Data from X-Bus Device to Host PCI_CLK LFRAME# LAD[3:0]# Start C+D Address TAR Sync=0110 Sync 0000 Data TAR Ax, nXCSx nXRD Data Valid Figure 12.14 - X-Bus and LPC I/O Read Cyle NOTE: Minimum read pulse width is shown. Rev. 0.5 (03-24-05) Page 228 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet 12.4.2.2 X-Bus I/O Write Cycle: LPC I/O Write Cycle - Data from Host to X-Bus Device PCI_CLK LFRAME# LAD[3:0]# Start C+D Address Data TAR Sync=0110 Sync 0000 TAR Ax, nXCSx nXWR Data Valid Figure 12.15 - X-Bus and LPC I/O Write Cycle NOTE: Minimum write pulse width is shown. SMSC SIO10N268 Page 229 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet 12.4.3 X-Bus Memory Cycle Timing The following timing values are based on a 33MHz PCI clock. Timing values will vary with variations in the PCI clock frequency. The following timing diagrams are designed to support Intel's 3 Volt Strata Flash Memory devices. 12.4.3.1 Timing For FWH and LPC initiated Memory Read Cycles with the X-Bus t1 XA[0:20] nXCS0 t2 t3 t4 t7 Valid Address t8 nXRD nXWR XD[0:7] t5 Valid Data t6 Figure 12.16 - X-Bus Memory Read NAME t1 t2 t3 t4 DESCRIPTION Valid Address Valid Address to Chip Select active Chip Select active to nXRD active nXRD active to nXRD inactive MIN 70 0 10 A: 60 B: 90 C: 120 D: 150 20 0 0 0 TYP MAX 30 40 A: 70 B: 100 C: 130 D: 160 30 10 UNITS ns ns ns ns t5 t6 t7 t8 Data Valid to nXRD inactive Data Hold following nXRD inactive nXRD inactive to Chip Select inactive Address Hold following Chip Select inactive ns ns ns ns Rev. 0.5 (03-24-05) Page 230 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet 12.4.3.2 Timing For FWH and LPC initiated Memory Write Cycles with the X-Bus t1 XA[0:20] t2 nXCS0 nXRD nXWR t4 t5 Valid Data t6 t3 t7 Valid Address t8 XD[0:7] Figure 12.17 - X-Bus Memory Write NAME t1 t2 t3 t4 DESCRIPTION Valid Address Valid Address to Chip Select active Chip Select active to nXWR active nXWR active to nXWR inactive MIN 80 0 10 A: 60 B: 90 C: 120 D: 150 10 10 10 0 TYP MAX 30 40 A: 70 B: 100 C: 130 D: 160 40 40 40 UNITS ns ns ns ns t5 t6 t7 t8 Data Valid to nXWR active Data Hold following nXWR inactive nXWR inactive to nXCS[x] inactive Address Hold following nXCS[x] inactive ns ns ns ns SMSC SIO10N268 Page 231 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet 12.5 Host Timing (ISA Mode Only) AX, AEN, nIOCS16 t2 nIOW t1 t4 t3 DATA (D0-D7) FINTR t5 DATA VALID t6 PINTR t7 PINTR is the interrupt assigned to the Parallel Port FINTR is the interrupt assigned to the Floppy Disk Parameter t1 t2 t3 t4 t5 t6 t7 A0-A9, AEN, nIOCS16 Set Up to nIOW Low nIOW Width A0-A9, AEN, nIOCS16 Hold from nIOW High Data Set Up Time to nIOW High Data Hold Time from nIOW High Write Strobe to Clear FINTR nIOW Inactive to PINTR Inactive min 40 150 10 40 10 typ max units ns ns ns ns ns ns ns 40 55 260 Figure 12.18 - Microprocessor Write Timing Rev. 0.5 (03-24-05) Page 232 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet t15 AEN t16 t3 t2 FDRQ, PDRQ FDACKX PDACKX t14 t11 nIOR or nIOW t6 t5 t8 t1 t4 t12 DATA (DO-D7) t7 DATA VALID t13 t10 t9 TC FDRQ refers to the DRQ assigned to the Floppy Disk PDRQ refers to the DRQ assigned to the Parallel Port FDACKX refers to the nDACK assigned to the to the Floppy Disk PDACKX refers to the nDACK assigned to the Parallel Port Parameter t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 nDACK Delay Time from FDRQ High DRQ Reset Delay from nIOR or nIOW FDRQ Reset Delay from nDACK Low nDACK Width nIOR Delay from FDRQ High nIOW Delay from FDRQ High Data Access Time from nIOR Low Data Set Up Time to nIOW High Data to Float Delay from nIOR High Data Hold Time from nIOW High nDACK Set Up to nIOW/nIOR Low nDACK Hold After nIOW/nIOR High TC Pulse Width AEN Set Up to nIOR/nIOW AEN Hold from nDACK TC Active to PDRQ Inactive min 0 typ max 100 100 units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 150 0 0 40 10 10 5 10 60 40 10 100 60 100 Figure 12.19 - DMA Timing SMSC SIO10N268 Page 233 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet 12.6 Floppy Disk Timing nDIR t3 nSTEP t9 nDS0-1 t4 t1 t2 t5 nINDEX t6 nRDATA t7 nWDATA t8 Figure 12.20 - Floppy Disk Drive Timing (AT Mode Only) NAME t1 t2 t3 t4 t5 t6 t7 t8 t9 Note 12.2 DESCRIPTION nDIR Set Up to STEP Low nSTEP Active Time Low nDIR Hold Time after nSTEP nSTEP Cycle Time MIN TYP 4 24 96 132 20 2 40 .5 MAX UNITS X (Note 12.2) X (Note 12.2) X (Note 12.2) X (Note 12.2) X (Note 12.2) X (Note 12.2) ns Y (Note 12.2) ns nDS0-1 Hold Time from nSTEP Low (Note 12.3) nINDEX Pulse Width nRDATA Active Time Low nWDATA Write Data Width Low nDS0-1, Setup Time nDIR Low (Note 12.3) 0 X specifies one MCLK period and Y specifies one WCLK period. MCLK = 16 x Data Rate (at 500 kb/s MCLK = 8 MHz) WCLK = 2 x Data Rate (at 500 kb/s WCLK = 1 MHz) The nDS0-1 setup and hold times must be met by software. Note 12.3 Rev. 0.5 (03-24-05) Page 234 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet 12.7 EPP Parallel Port Timing t1 nWRITE t3 PD<7:0> t4 t5 t6 nDATASTB nADDRSTB t8 nWAIT Figure 12.21 - EPP 1.9 Data or Address Write Cycle NAME t1 t2 t3 t4 t5 t6 t7 DESCRIPTION nWAIT Asserted to nWRITE Asserted (Note 12.4) nWAIT Asserted to nWRITE Change (Note 12.4) nWAIT Asserted to PDATA Invalid (Note 12.4) PDATA Valid to Command Asserted nWRITE to Command Asserted nWAIT Asserted to Command Asserted (Note 12.4) nWAIT Deasserted to Command Deasserted (Note 12.4) Command Asserted to nWAIT Deasserted Command Deasserted to nWAIT Asserted MIN 60 60 0 10 5 60 60 TYP MAX 185 185 UNITS ns ns ns ns ns ns ns t2 t7 t9 35 210 190 10 t8 t9 Note 12.4 0 0 s ns nWAIT must be filtered to compensate for ringing on the parallel bus cable. WAIT is considered to have settled after it does not transition for a minimum of 50 nsec. SMSC SIO10N268 Page 235 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet t1 nWRITE t3 PD<7:0> t7 t8 t9 nDATASTB nADDRSTB t11 nWAIT Figure 12.22 - EPP 1.9 Data or Address Read Cycle NAME DESCRIPTION t1 nWAIT Asserted to nWRITE Deasserted t2 nWAIT Asserted to nWRITE Modified (Note 12.5, Note 12.6) t3 nWAIT Asserted to PDATA Hi-Z (Note 12.5) t4 Command Asserted to PDATA Valid t5 Command Deasserted to PDATA Hi-Z t6 nWAIT Asserted to PDATA Driven (Note 12.5) t7 PDATA Hi-Z to Command Asserted t8 nWRITE Deasserted to Command t9 nWAIT Asserted to Command Asserted t10 nWAIT Deasserted to Command Deasserted (Note 12.5) t11 PDATA Valid to nWAIT Deasserted t12 PDATA Hi-Z to nWAIT Asserted Note 12.5 Note 12.6 MIN 0 60 TYP MAX 185 190 t2 t4 t5 t6 t10 t12 UNITS ns ns 60 0 0 60 0 1 0 60 0 0 180 190 30 195 180 ns ns ns ns ns ns ns ns ns s nWAIT is considered to have settled after it does not transition for a minimum of 50 ns. When not executing a write cycle, EPP nWRITE is inactive high. Rev. 0.5 (03-24-05) Page 236 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet t1 nWRITE t2 PD<7:0> t3 t4 nDATASTB nADDRSTB t5 nWAIT Figure 12.23 - EPP 1.7 Data or Address Write Cycle NAME t1 t2 t3 t4 t5 DESCRIPTION Command Deasserted to nWRITE Change Command Deasserted to PDATA Invalid PDATA Valid to Command Asserted nWRITE to Command Command Deasserted to nWAIT Deasserted MIN 0 50 10 5 0 TYP MAX 40 UNITS ns ns ns ns ns 35 35 nWRITE t1 PD<7:0> nDATASTB nADDRSTB t3 nWAIT Figure 12.24 - EPP 1.7 Data or Address Read Cycle NAME DESCRIPTION t1 Command Asserted to PDATA Valid t2 Command Deasserted to PDATA Hi-Z t3 Command Deasserted to nWAIT Deasserted MIN TYP MAX UNITS ns ns ns t2 0 0 0 SMSC SIO10N268 Page 237 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet 12.8 ECP Parallel Port Timing 12.8.1 Parallel Port FIFO (Mode 101) The standard parallel port is run at or near the peak 500KBytes/sec allowed in the forward direction using DMA. The state machine does not examine nACK and begins the next transfer based on Busy. Refer to Figure 12.25. 12.8.2 ECP Parallel Port Timing The timing is designed to allow operation at approximately 2.0 Mbytes/sec over a 15ft cable. If a shorter cable is used then the bandwidth will increase. 12.8.3 Forward-Idle When the host has no data to send it keeps HostClk (nStrobe) high and the peripheral will leave PeriphClk (Busy) low. 12.8.4 Forward Data Transfer Phase The interface transfers data and commands from the host to the peripheral using an interlocked PeriphAck and HostClk. The peripheral may indicate its desire to send data to the host by asserting nPeriphRequest. The Forward Data Transfer Phase may be entered from the Forward-Idle Phase. While in the Forward Phase the peripheral may asynchronously assert the nPeriphRequest (nFault) to request that the channel be reversed. When the peripheral is not busy it sets PeriphAck (Busy) low. The host then sets HostClk (nStrobe) low when it is prepared to send data. The data must be stable for the specified setup time prior to the falling edge of HostClk. The peripheral then sets PeriphAck (Busy) high to acknowledge the handshake. The host then sets HostClk (nStrobe) high. The peripheral then accepts the data and sets PeriphAck (Busy) low, completing the transfer. This sequence is shown in Figure 12.26. The timing is designed to provide 3 cable round-trip times for data setup if Data is driven simultaneously with HostClk (nStrobe). 12.8.5 Reverse-Idle Phase The peripheral has no data to send and keeps PeriphClk high. The host is idle and keeps HostAck low. 12.8.6 Reverse Data Transfer Phase The interface transfers data and commands from the peripheral to the host using an interlocked HostAck and PeriphClk. The Reverse Data Transfer Phase may be entered from the Reverse-Idle Phase. After the previous byte has beed accepted the host sets HostAck (nALF) low. The peripheral then sets PeriphClk (nACK) low when it has data to send. The data must be stable for the specified setup time prior to the falling edge of PeriphClk. When the host is ready to accept a byte it sets HostAck (nALF) high to acknowledge the Rev. 0.5 (03-24-05) Page 238 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet handshake. The peripheral then sets PeriphClk (nACK) high. After the host has accepted the data it sets HostAck (nALF) low, completing the transfer. This sequence is shown in Figure 12.27. 12.8.7 Output Drivers To facilitate higher performance data transfer, the use of balanced CMOS active drivers for critical signals (Data, HostAck, HostClk, PeriphAck, PeriphClk) are used in ECP Mode. Because the use of active drivers can present compatibility problems in Compatible Mode (the control signals, by tradition, are specified as open-drain), the drivers are dynamically changed from open-drain to push-pull. The timing for the dynamic driver change is specified in then IEEE 1284 Extended Capabilities Port Protocol and ISA Interface Standard, Rev. 1.14, July 14, 1993, available from Microsoft. The dynamic driver change must be implemented properly to prevent glitching the outputs. t6 t3 PD<0:7> t1 t2 t5 nSTROBE t4 BUSY Figure 12.25 - Parallel Port FIFO Timing NAME t1 t2 t3 t4 t5 t6 Note 12.7 DESCRIPTION PDATA Valid to nSTROBE Active nSTROBE Active Pulse Width PDATA Hold from nSTROBE Inactive (Note 12.7) nSTROBE Active to BUSY Active BUSY Inactive to nSTROBE Active BUSY Inactive to PDATA Invalid (Note 12.7) MIN 600 600 450 TYP MAX UNITS ns ns ns ns ns ns 500 680 80 The data is held until BUSY goes inactive or for time t3, whichever is longer. This only applies if another data transfer is pending. If no other data transfer is pending, the data is held indefinitely. SMSC SIO10N268 Page 239 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet t3 nALF t4 PD<7:0> t2 t1 t7 nSTROBE BUSY t6 t5 t6 t8 Figure 12.26 - ECP Parallel Port Forward Timing NAME DESCRIPTION t1 nALF Valid to nSTROBE Asserted t2 PDATA Valid to nSTROBE Asserted t3 BUSY Deasserted to nALF Changed (Note 12.8, Note 12.9) t4 BUSY Deasserted to PDATA Changed (Note 12.8, Note 12.9) t5 nSTROBE Asserted to Busy Asserted t6 nSTROBE Deasserted to Busy Deasserted t7 BUSY Deasserted to nSTROBE Asserted (Note 12.8, Note 12.9) t8 BUSY Asserted to nSTROBE Deasserted (Note 12.9) Note 12.8 Note 12.9 MIN 0 0 80 TYP MAX 60 60 180 UNITS ns ns ns 80 0 0 80 80 180 ns ns ns ns ns 200 180 Maximum value only applies if there is data in the FIFO waiting to be written out. BUSY is not considered asserted or deasserted until it is stable for a minimum of 75 to 130 ns. Rev. 0.5 (03-24-05) Page 240 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet t2 PD<7:0> t1 t5 nACK t4 nALF Figure 12.27 - ECP Parallel Port Reverse Timing NAME DESCRIPTION t1 PDATA Valid to nACK Asserted t2 nALF Deasserted to PDATA Changed t3 nACK Asserted to nALF Deasserted (Note 12.10, Note 12.11) t4 nACK Deasserted to nALF Asserted (Note 12.11) t5 nALF Asserted to nACK Asserted t6 nALF Deasserted to nACK Deasserted MIN 0 0 80 TYP MAX UNITS ns ns ns t6 t3 t4 200 200 80 0 0 ns ns ns Note 12.10 Maximum value only applies if there is room in the FIFO and terminal count has not been received. ECP can stall by keeping nALF low. Note 12.11 nACK is not considered asserted or deasserted until it is stable for a minimum of 75 to 130 ns. SMSC SIO10N268 Page 241 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet 12.9 IR Timing DATA 0 t2 t1 IRRX n IRRX t2 t1 1 0 1 0 0 1 1 0 1 1 Pa rame ter t1 t1 t1 t1 t1 t1 t1 t2 t2 t2 t2 t2 t2 t2 Pulse Width at 1 15kba ud Pul se Wid th at 57.6kba ud Pul se Wid th at 38.4kba ud Pul se Wid th at 19.2kba ud Pu lse Wi dth a t 9.6kba ud Pu lse Wi dth a t 4.8kba ud Pu lse Wi dth a t 2.4kba ud Bit Time at 1 15kba ud Bit Time at 57.6kba ud Bit Time at 38.4kba ud Bit Time at 19.2kba ud Bi t Ti me a t 9.6kba ud Bi t Ti me a t 4.8kba ud Bi t Ti me a t 2.4kba ud min 1.4 1.4 1.4 1.4 1.4 1.4 1.4 ty p 1.6 3.22 4.8 9.7 19.5 39 78 8.68 17.4 26 52 1 04 2 08 4 16 m ax 2.71 3.69 5.53 1 1.07 2 2.13 4 4.27 8 8.55 units s s s s s s s s s s s s s s No te s: 1. Recei ve Pu lse Detection C ri te ria: A re ceived p ulse is consi dered d etecte d if the receive d p ulse is a mini mum o f 1.41 s. 2. IR RX: L5, CRF1 Bit 0 = 1 nIRRX: L5, CRF1 Bi t 0 = 0 (defaul t) Figure 12.28 - IrDA Receive Timing Rev. 0.5 (03-24-05) Page 242 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet DAT A 0 t2 t1 1 0 1 0 0 1 1 0 1 1 t2 t1 IRT X n IRT X Parameter t1 t1 t1 t1 t1 t1 t1 t2 t2 t2 t2 t2 t2 t2 Pulse Width at 115kbaud Pulse Widt h at 57. 6kbaud Pulse Widt h at 38. 4kbaud Pulse Widt h at 19. 2kbaud Pulse Widt h at 9. 6kbaud Pulse Widt h at 4. 8kbaud Pulse Widt h at 2. 4kbaud Bit T ime at 115kbaud Bit Time at 57.6kbaud Bit Time at 38.4kbaud Bit Time at 19.2kbaud Bit Tim e at 9.6kbaud Bit Tim e at 4.8kbaud Bit Tim e at 2.4kbaud mi n 1.41 1.41 1.41 1.41 1.41 1.41 1.41 typ 1.6 3.22 4.8 9.7 19.5 39 78 8.68 17.4 26 52 104 208 416 max 2.71 3.69 5.53 11.07 22.13 44.27 88.55 u nits s s s s s s s s s s s s s s Notes: 1. IrDA @ 115k i s HPSIR com pati ble. IrDA @ 2400 wi ll al low compatibilit y with HP95LX and 48SX. 2. IRT X: L5, CRF 1 Bit 1 = 1 (default) nI RT X: L5, CRF1 Bit 1 = 0 Figure 12.29 - IrDA Transmit Timing SMSC SIO10N268 Page 243 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet DA A T 0 t1 IRRX n IRRX 1 t2 0 1 0 0 1 1 0 1 1 t3 M IRRX t5 t4 nM IRRX t6 Pa ramet er t1 t2 t3 t4 t5 t6 M odu lated Out put Bit T ime Off Bit Time M odu lated Outp ut " On" M odu lated Out put " Off" M odu lated Outp ut " On" M odu lated Out put " Off" min typ max units s s 0.8 0.8 0.8 0.8 1 1 1 1 1.2 1.2 1.2 1.2 s s s s Note s: 1 . IRRX: L 5, CRF 1 Bit 0 = 1 n IRRX: L5 , CRF 1 Bit 0 = 0 (de fault) M IRRX, nMI RRX are the mod ulate d ou tpu ts Figure 12.30 - Amplitude Shift Keyed IR Receive Timing Rev. 0.5 (03-24-05) Page 244 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet DATA 0 t1 1 t2 0 1 0 0 1 1 0 1 1 IRTX n IRT X t3 MIRTX t5 n MIRT X t4 t6 Pa ramet er t1 t2 t3 t4 t5 t6 M odu lated Out put Bit T ime Off Bit T ime M odu lated Outp ut " On" M odu lated Outp ut " Off" M odu lated Outp ut " On" M odu lated Outp ut " Off" min t yp max units s s 0.8 0.8 0.8 0.8 1 1 1 1 1.2 1.2 1.2 1.2 s s s s Note s: 1 . IRT X : L5 , CRF 1 Bit 1 = 1 (def ault) nI RTX: L 5, CRF1 Bit 1 = 0 MIRTX, nM IRTX a re the mod ulate d ou tpu ts Figure 12.31 - Amplitude Shift Keyed IR Transmit Timing 12.10 Serial IRQ Timing PCI_CLK t1 SER_IRQ Figure 12.32 - Setup and Hold Time NAME t1 t2 DESCRIPTION SER_IRQ Setup Time to PCI_CLK Rising SER_IRQ Hold Time to PCI_CLK Rising MIN 7 0 TYP MAX UNITS nsec nsec t2 SMSC SIO10N268 Page 245 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet 12.11 UART Timing Data Start TXD1, 2 Data (5-8 Bits) t1 Parity Stop (1-2 Bits) Figure 12.33 - Serial Port Data NAME t1 DESCRIPTION Serial Port Data Bit Time MIN TYP tBR (Note 12.12) MAX UNITS nsec Note 12.12 tBR is 1/Baud Rate. The Baud Rate is programmed through the divisor latch registers. Baud Rates have percentage errors indicated in the "Baud Rate" table in the "Serial Port" section. Rev. 0.5 (03-24-05) Page 246 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet Chapter 13 XNOR-Chain Test Mode The SIO10N268 provides board test capability through the implementation of XNOR chain. See following sub-sections. XNOR-Chain test structure allows users to confirm that all pins are in contact with the motherboard during assembly and test operations. See Figure 13.1 below. When the chip is in the XNOR chain test mode, setting the state of any of the input pins to the opposite of its current state will cause the output of the chain to toggle. The XNOR-Chain test structure must be activated to perform these tests. When the XNOR-Chain is activated, the SIO10N268 pin functions are disconnected from the device pins, which all become input pins except for one output pin at the end of XNOR-Chain. The tests that are performed when the XNOR-Chain test structure is activated require the board-level test hardware to control the device pins and observe the results at the XNOR-Chain output pin. I/O#1 I/O#2 I/O#3 I/O#n XNor Out Figure 13.1 - XNOR-Chain Test Structure 13.1 Entering and Exiting Test Mode To place a device into Test Mode, procedures should be followed according to the state of the LPC_ISA pin. That means if the LPC_ISA pin is left unconnected or is grounded, the device should be put into test mode using the procedures for LPC Mode. If the LPC_ISA pin is tied to VCC, the device should be put into test mode using the procedures for ISA Mode. XNOR-Chain test mode can be entered as follows: Devices configured for LPC Mode (default - LPC_ISA pin is unconnected or tied to ground): - On the rising (deasserting) edge of PCI_RESET#, drive LFRAME# low and drive LAD[0] low. Devices configured for ISA Mode (LPC_ISA pin is tied to VCC): - On the falling (deasserting) edge of RESET_DRV, drive nIORD low and drive nIOWR low. SMSC SIO10N268 Page 247 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet Exit XNOR-Chain test mode as follows: Devices configured for LPC Mode: - On the rising (deasserting) edge of PCI_RESET#, drive either LFRAME# or LAD[0] high. Devices configured for ISA Mode: - On the falling (deasserting) edge of RESET_DRV, drive either nIORD or nIOWR high The PCI_RESET#, nRESET_DRV, and LPC_ISA pins are not included in the XNOR-Chain. The XNORChain output pin# is 18, nIO_PME. See the following subsections for more details. 13.2 Pin List of XNOR Chain Pins 1 to 128 on the chip are inputs to the first XNOR chain, with the exception of the following: 1) 2) 3) 4) 5) VCC (pins 25, 49, 70, 102, and 126) and VTR (pin 19). VSS (pins 7, 27, 52, 74, and 109). PCI_RESET# (pin 29), RESET_DRV (pin 59) LPC_ISA (pin 54) nIO_PME (pin 18) This is the chain output. To put the chip in the first XNOR chain test mode: LPC_Mode: Tie LAD0 (pin 21) and LFRAME# (pin 26) low. Then toggle PCI_RESET# (pin 29) from a low to a high state. Once the chip is put into XNOR chain test mode, LAD0 (pin 21) and LFRAME# (pin 26) become part of the chain. ISA_Mode: Tie nIORD (pin 100) and nIOWR (pin 101) low. Then toggle RESET_DRV (pin 59) from a high to a low state. Once the chip is put into XNOR chain test mode, nIORD (pin 100) and nIOWR (pin 101) become part of the chain. To exit the first XNOR chain test mode: Devices configured for LPC Mode (default - LPC_ISA pin is unconnected or tied to ground): - Tie LAD0 (pin 21) or LFRAME# (pin 26) high. Then toggle PCI_RESET# (pin 29) from a low to a high state. Devices configured for ISA Mode (LPC_ISA pin is tied to VCC): - Tie nIORD (pin 100) or nIOWR (pin 101) high. Then toggle RESET_DRV (pin 59) from a high to a low state. NOTE: A VCC POR will also cause the XNOR chain test mode to be exited, regardless of the Mode. To verify the test mode has been exited, observe the output at nIO_PME (pin 18). Toggling any of the input pins in the chain should not cause its state to change. 13.3 Setup of XNOR Chain WARNING: Ensure power supply is off during setup. 1) 2) Connect VSS (pins 7, 27, 52, 74, and 109) to ground. Connect VCC (pins 25, 49, 70, 102, and 126) and VTR (pin 19) to VCC (3.3V). Rev. 0.5 (03-24-05) Page 248 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet 3) 4) Connect test equipment to monitor output on nIO_PME (pin 18). The LPC_ISA pin should be left unconnected or tied directly to ground if the device is implemented in LPC Mode. The LPC_ISA pin should be connected directly to VCC for devices that are implemented in ISA Mode. If configured for LPC Mode, tie nLRESET and RESET_DRV/XA16 to ground. If configured for ISA Mode, tie RESET_DRV to VCC and tie nLRESET to ground. All other pins should be tied to ground. 5) 6) 13.4 Testing Procedure 1) 2) Turn power on. Enter test mode as defined in section 13.1 Entering and Exiting Test Mode. The chip is now in XNOR chain test mode. At this point, all inputs to the first XNOR chain are low. The output, on nIO_PME (pin 18), should be high. Refer to INITIAL CONFIG on TRUTH TABLE 1. Bring pin 128 high. The output on nIO_PME (pin 18) should toggle (i.e., nIO_PME = low). Refer to STEP ONE on TRUTH TABLE 1. In descending pin order, bring each input high. The output should switch states each time an input is toggled. Continue until all inputs are high. The output on nIO_PME should now be low. Refer to END CONFIG on TRUTH TABLE 1. The current state of the chip is now represented by INITIAL CONFIG in TRUTH TABLE 2. Each input should now be brought low, starting at pin one and continuing in ascending order. Continue until all inputs are low. The nIO_PME output should now be high. Refer to TRUTH TABLE 2. To exit test mode follow the procedures outlined in section 13.1 Entering and Exiting Test Mode. 3) 4) 5) 6) 7) SMSC SIO10N268 Page 249 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet TRUTH TABLE 1 - Toggling Inputs in Descending Order PIN 128 PIN 127 PIN 125 PIN 124 PIN 123 L PIN ... L PIN 1 L OUTPUT PIN 18 H INITIAL CONFIG STEP 1 STEP 2 STEP 3 STEP 4 STEP 5 ... STEP N-1 END CONFIG L H H H H H ... H H L L H H H H ... H H L L L H H H ... H H L L L L H H ... H H L L L L H ... H H L L L L L ... H H L L L L L ... L H L H L H L ... H L TRUTH TABLE 2 - Toggling Inputs in Ascending Order PIN 1 H PIN 2 H PIN 3 H PIN 4 H PIN 5 H PIN ... H PIN 128 H OUTPUT PIN 18 L INITIAL CONFIG STEP 1 STEP 2 STEP 3 STEP 4 STEP 5 STEP N-1 END CONFIG L L L L L ... L L H L L L L ... L L H H L L L ... L L H H H L L ... L L H H H H L ... L L H H H H H ... L L H H H H H ... H L H L H L H ... L H Rev. 0.5 (03-24-05) Page 250 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet Chapter 14 Package Outline 14.1 128 Pin TQFP Package Outline, 14x14x1.0 Body, 2 MM Footprint A A1 A2 D D1 E E1 H L L1 e W R1 R2 ccc MIN ~ 0.05 0.95 15.80 13.80 15.80 13.80 0.09 0.45 ~ 0o 0.13 0.08 0.08 ~ NOMINAL ~ ~ ~ ~ ~ ~ ~ ~ 0.60 1.00 0.40 Basic ~ 0.18 ~ ~ ~ MAX 1.20 0.15 1.05 16.20 14.20 16.20 14.20 0.20 0.75 ~ 7o 0.23 ~ 0.20 0.08 REMARKS Overall Package Height Standoff Body Thickness X Span X body Size Y Span Y body Size Lead Frame Thickness Lead Foot Length Lead Length Lead Pitch Lead Foot Angle Lead Width Lead Shoulder Radius Lead Foot Radius Coplanarity SMSC SIO10N268 Page 251 Rev. 0.5 (03-24-05) DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet NOTES: 1 Controlling Unit: millimeter. Tolerance on the true position of the leads is 0.035 mm maximum. 2 3 Package body dimensions D1 and E1 do not include the mold protrusion. Maximum mold protrusion is 0.25 mm. Dimension for foot length L measured at the gauge plane 0.25 mm above the seating plane. Details of pin 1 identifier are optional but must be located within the zone indicated. 4 5 Rev. 0.5 (03-24-05) Page 252 SMSC SIO10N268 DATASHEET Advanced Notebook I/O for ISA or LPC Designs Datasheet Chapter 15 References 1) 2) 3) 4) 5) SMSC Infrared Communications Controller (IrCC) Specification, dated 5/10/96 IEEE 1284 Extended Capabilities Port Protocol and ISA Standard, Rev. 1.14, July 14, 1993. PCI Bus Power Management Interface Specification, Rev. 1.0, Draft, March 18, 1997. Low Pin Count (LPC) Interface Specification, Revision 1.0, September 29, 1997, Intel Document. Advanced Configuration and Power interface Specification, Revision 1.0 SMSC SIO10N268 Page 253 Rev. 0.5 (03-24-05) DATASHEET |
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